Consider the MOSFET diff-amp with the configuration in Figure P11.33. The circuit parameters are V + = 3 V , V − = − 3 V , and I Q = 0.2 mA k n ′ = 100 μ A / V 2 , W / L = 10 , and λ = 0. The range of the common mode input voltage is to be − 1.5 ≤ v c m ≤ + 1.5 V , and the common mode rejection ratio is to be CMRR dB = 50 dB . (a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. (b) Design an all MOSFET current source to produce the desired bias current and CMRR. The minimum W / L ratio of any transistor is to be 0.8 and assume λ = 0.02 V − 1 for all transistors in the current source circuit.
Consider the MOSFET diff-amp with the configuration in Figure P11.33. The circuit parameters are V + = 3 V , V − = − 3 V , and I Q = 0.2 mA k n ′ = 100 μ A / V 2 , W / L = 10 , and λ = 0. The range of the common mode input voltage is to be − 1.5 ≤ v c m ≤ + 1.5 V , and the common mode rejection ratio is to be CMRR dB = 50 dB . (a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. (b) Design an all MOSFET current source to produce the desired bias current and CMRR. The minimum W / L ratio of any transistor is to be 0.8 and assume λ = 0.02 V − 1 for all transistors in the current source circuit.
Solution Summary: The value of the quiescent drain current of transistors one and two is calculated as BeginarraycI_Q2 = 0.
Consider the MOSFET diff-amp with the configuration in Figure P11.33. The circuit parameters are
V
+
=
3
V
,
V
−
=
−
3
V
,
and
I
Q
=
0.2
mA
k
n
′
=
100
μ
A
/
V
2
,
W
/
L
=
10
,
and
λ
=
0.
The range of the common mode input voltage is to be
−
1.5
≤
v
c
m
≤
+
1.5
V
,
and the common mode rejection ratio is to be
CMRR
dB
=
50
dB
. (a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. (b) Design an all MOSFET current source to produce the desired bias current and CMRR. The minimum
W
/
L
ratio of any transistor is to be 0.8 and assume
λ
=
0.02
V
−
1
for all transistors in the current source circuit.
53. Obtain an expression for i(t) as labeled in the circuit diagram of Fig. 8.84, and
determine the power being dissipated in the 40 2 resistor at t = 2.5 ms.
t=0
i(t)
30 Ω
w
200 mA 4002
30 m
100 mA(
7.2
At t = 0, the switch in the circuit shown moves
instantaneously from position a to position b.
a) Calculate v, for t≥ 0.
b) What percentage of the initial energy stored
in the inductor is eventually dissipated in
the 4
resistor?
6Ω
a
w
+
10 0.32 H3 403
6.4 A
=0
b
Answer: (a) -8e-10 V, t = 0;
(b) 80%.
At t = 0, the switch closes. Find the IL(t) and VL(t) for t≥ 0 in t and s domain.
Can you help me?
1)
(+.
24V
ง
Anahtar t=0 anında kapatılıyor.
to icin TL(t) ve
bulunuz.
J
3√√√2
ww
مفروم
+
t=0
$6.5 5H VLCH) 2.2
Vilt)
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