Chapter 11, Problem 11.13TYU

Redesign the circuit in Figure 11.30 using a Widlar current source and bias voltages of $\pm 5\text{V}$ . The bias current $I_Q$ is to be no less than $100\mu \text{A}$ and the total power dissipated in the circuit (including the current-source circuit) is to be no more than $10\text{mW}$ . The diff-amp transistor parameters are the same as in Exercise $\text{Ex}11.10$ . The circuit is to provide a minimum loading effect when a second stage with an input resistance of $R=90\text{k}\Omega$ is connected to the diff-amp. Determine the differentialI mode voltage gain for this circuit. (Ans. $R_1=10.3\text{k}\Omega ,R_E=0.571\text{k}\Omega ,A_d=158$ ).