The circuit parameters of the diff-amp shown in Figure 11.2 are V + = 3 V , V − = − 3 V , and I Q = 0.25 mA . Base currents are negligible and V A = ∞ for each transistor. (a) Design the circuit such that a differential-mode output voltage of v o = v C 1 − v C 2 = 1.2 V is produced when a differential-mode input voltage of v d = v 1 − v 2 = 16 mV is applied. (b) What is the maximum possible common-mode input voltage that can be applied such that the input transistors remain biased in the forward-active mode? (c) For a one-sided output, what is the value of CMRR dB if the output resistance of the current source is R o = 4 M Ω ?
The circuit parameters of the diff-amp shown in Figure 11.2 are V + = 3 V , V − = − 3 V , and I Q = 0.25 mA . Base currents are negligible and V A = ∞ for each transistor. (a) Design the circuit such that a differential-mode output voltage of v o = v C 1 − v C 2 = 1.2 V is produced when a differential-mode input voltage of v d = v 1 − v 2 = 16 mV is applied. (b) What is the maximum possible common-mode input voltage that can be applied such that the input transistors remain biased in the forward-active mode? (c) For a one-sided output, what is the value of CMRR dB if the output resistance of the current source is R o = 4 M Ω ?
Solution Summary: The author explains the design of the circuit fulfilling the given conditions. The base currents are negligible and V_A=infty.
The circuit parameters of the diff-amp shown in Figure 11.2 are
V
+
=
3
V
,
V
−
=
−
3
V
,
and
I
Q
=
0.25
mA
.
Base currents are negligible and
V
A
=
∞
for each transistor. (a) Design the circuit such that a differential-mode output voltage of
v
o
=
v
C
1
−
v
C
2
=
1.2
V
is produced when a differential-mode input voltage of
v
d
=
v
1
−
v
2
=
16
mV
is applied. (b) What is the maximum possible common-mode input voltage that can be applied such that the input transistors remain biased in the forward-active mode? (c) For a one-sided output, what is the value of
CMRR
dB
if the output resistance of the current source is
R
o
=
4
M
Ω
?
(b)
Below is a FSM with a 1-bit input A, and a 1-bit output Y. Deter-
mine the combined state and output table. Identify the unreachable states, and
sketch the state-transition diagram. In your table and diagram, use Os and 1s
for the states and next states, not symbols like S0, S1, etc.
A
D
D
D
CLK
S'₁₂
S2
S₁₁ S1
Y
S'
r
So
S2
S₁
So
reset
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