Consider the MOSFET diff-amp with the configuration in Figure P11.33. The circuit parameters are V + = 3 V , V − = − 3 V , and I Q = 0.2 mA k n ′ = 100 μ A / V 2 , W / L = 10 , and λ = 0. The range of the common mode input voltage is to be − 1.5 ≤ v c m ≤ + 1.5 V , and the common mode rejection ratio is to be CMRR dB = 50 dB . (a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. (b) Design an all MOSFET current source to produce the desired bias current and CMRR. The minimum W / L ratio of any transistor is to be 0.8 and assume λ = 0.02 V − 1 for all transistors in the current source circuit.
Consider the MOSFET diff-amp with the configuration in Figure P11.33. The circuit parameters are V + = 3 V , V − = − 3 V , and I Q = 0.2 mA k n ′ = 100 μ A / V 2 , W / L = 10 , and λ = 0. The range of the common mode input voltage is to be − 1.5 ≤ v c m ≤ + 1.5 V , and the common mode rejection ratio is to be CMRR dB = 50 dB . (a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. (b) Design an all MOSFET current source to produce the desired bias current and CMRR. The minimum W / L ratio of any transistor is to be 0.8 and assume λ = 0.02 V − 1 for all transistors in the current source circuit.
Solution Summary: The value of the quiescent drain current of transistors one and two is calculated as BeginarraycI_Q2 = 0.
Consider the MOSFET diff-amp with the configuration in Figure P11.33. The circuit parameters are
V
+
=
3
V
,
V
−
=
−
3
V
,
and
I
Q
=
0.2
mA
k
n
′
=
100
μ
A
/
V
2
,
W
/
L
=
10
,
and
λ
=
0.
The range of the common mode input voltage is to be
−
1.5
≤
v
c
m
≤
+
1.5
V
,
and the common mode rejection ratio is to be
CMRR
dB
=
50
dB
. (a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. (b) Design an all MOSFET current source to produce the desired bias current and CMRR. The minimum
W
/
L
ratio of any transistor is to be 0.8 and assume
λ
=
0.02
V
−
1
for all transistors in the current source circuit.
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