Chapter 11, Problem D11.73P

An all-CMOS diff-amp, including the current source circuit, with the configuration in Figure 11.32 is to be designed to have a differential-mode gain of $A_d=240.$ The bias voltages are $V^{+}=3\text{V}$ and $V^{-}=-3\text{V}.$ The total power dissipation in the circuit is to be limited to $0.8\text{mW}$ . Assume the NMOS transistor parameters are $V_{TN}=0.4\text{V},k_n^{\prime }=100\mu \text{A}/{\text{V}}^2,$ and ${\lambda }_n=0.02{\text{V}}^{-1}.$ Assume PMOS transistor parameters of $V_{TP}=-0.4\text{V}$ $k_p^{\prime }=40\mu \text{A}/{\text{V}}^2,$ and ${\lambda }_p=0.03{\text{V}}^{-1}$ .