Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Expert Solution & Answer
Chapter 6.6, Problem 6.21PP
Explanation of Solution
Estimating time in CPU cycles:
It is given that the sustained throughput using large strides from L1 is: 12,000 MB/s.
Clock frequency= 2,100 MHz
Individual read accesses= 8-byte long
Hence, one can estimate that it takes roughly
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solutionStudents have asked these similar questions
(c) The following Sigma 16 program has been loaded into memory at address 0000:
load R3,y[RO]
load R4,x[RO]
lea R5, 2[RO]
sub R1,R4,R3
mul R2,R1,R5
store R2,w[RO]
trap RO,RO,RO
x data 10
y data 12
w data 0
Show the content of the memory writing hexadecimal representation and using a
table with 3 columns: the memory address, the contents of that memory address,
and an explanation of what "the content (of that memory address) means". As a
reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c.
And here the opcodes for RX instructions: lea 0, load 1, store 2.
[7]
subject : computer architectures and organization (computer science)
Problem
Question 03 (CO3) [0.5 + 0.5 = 1]: Given below are the contents of several Intel 8086 registers
and PHYSICAL memory addresses (ALL in hexadecimal):
Registers:
Memory Locations [Physical Address] = Contents
[05000] = 3300
[06000] = 4444
[07000] = 5555
[95000] = 367A
[96000] = 6666
[97000] = 10C5
DI = 3000
%3D
BX = 3000
%3D
ВР 3 С345
For the following instructions, determine the contents of AX after the each of the instruction has
been executed:
(а) MOV
(b) MOV
АХ, ВР
АХ, [ВХ+DI]
AX =
AX
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
Knowledge Booster
Similar questions
- Problem 1.8 The following code segment, consisting of six instructions, needs to be executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I) xC(I) for 0 ≤ I ≤ 63. Load R1, B(I) /R1 - Memory (a + I)/ Load R2, C(I) Multiply R1, R2 Load R3, A(I) Add R3, R1 Store D(I), R3 t /R2 Memory (8 + 1)/ /R1 - (R1) × (R2)/ /R3 - Memory (7 + I)/ - /R3 (R3) + (R1)/ /Memory (0 + I) ← (R3)/ where R1, R2, and R3 are CPU registers, (R1) is the content of R1, a, ß,7, and are the starting memory addresses of arrays B(1), C(I), A(I), and D(I), respectively. Assume four clock cycles for each Load or Store, two cycles for the Add, and eight cycles for the Multiply on either a uniprocessor or a single PE in an SIMD machine. (a) Calculate the total ber of CPU cycles needed to execute the above code seg- ment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring all other time delays. (b) Consider the use of an SIMD computer with 64 PEs to execute the above…arrow_forwardQuestion 4: a) Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and jare in registers $80, $s 1, $t0, and $t1, respectively. Also, assume that register $s2 holds the base address of array D. for (i=0; iarrow_forwardProblem 1.8 The following code segment, consisting of six instructions, needs to be executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I) xC(I) for 0 ≤ I≤ 63. Load R1, B(I) /R1 - Memory (a + I)/ Load R2, C(I) Multiply R1, R2 Load R3, A(I) Add R3, R1 Store D(I), R3 t /R2 Memory (8 + 1)/ /R1 - (R1) × (R2)/ /R3 - Memory (7 + I)/ - /R3 (R3) + (R1)/ /Memory (0 + I) ← (R3)/ where R1, R2, and R3 are CPU registers, (R1) is the content of R1, a, ß,7, and are the starting memory addresses of arrays B(1), C(I), A(I), and D(I), respectively. Assume four clock cycles for each Load or Store, two cycles for the Add, and eight cycles for the Multiply on either a uniprocessor or a single PE in an SIMD machine. (a) Calculate the total ber of CPU cycles needed to execute the above code seg- ment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring all other time delays. (b) Consider the use of an SIMD computer with 64 PEs to execute the above…arrow_forward(e) Instruction(s) to copy contents at one memory location to another: C[g] =A[i+j-3). Assume i, j,g values are in registers x5, x6, x7. Assume base address in memory of Array data structures 'A, B' (or address in memory of 'A[O]' and 'B[O]') are stored in Registers x28, 29• In RISCV, only load and store instructions access memory locations • These instructions must follow a 'format' to access memory • Assume a 32 bit machine in all problems unless asked to assume otherwisearrow_forward[1] ( Show your work. Show hoe you compute memory address by using the effective memory address computation. Assume the following values are stored at the indicated memory addresses and registers: Address Value 0x100 OxFF 0x104 OxAB 0x108 0x13 0x10c 0x11 Register %rax %rcx %rdx $0x108 (%rax) 4(%rax) 9(%rax, %rdx) 260(%rcx,%rdx) OxFC (,%rcx, 4) (%rax, %rdx, 4) Value 0x100 0x1 0x3 Fill in the following table showing the values for the indicated operands: Operand Value %rax 0x104arrow_forward(c) Assume that a Direct Mapping Function is apply on a memory system with 24-bit address. The cache has 16384 blocks, each storing 4 words. Calculate its tag, block, and word size.arrow_forwardDO B part if do able A Instruction Set Architecture A.1 Instruction set We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a. LOAD a, b a <- b STOR a, b a <- b ADD a, b, c a <- b + c ASH a, b, c a <- (b >>[s] c) LSH a, b, c a <- (b >>[u] c) BR a PC <- a SUB a, b, c a <- b - c BEQ a, b, c PC <- a if b = c MUL a, b, c a <- b * c BNE a, b, c PC <- a if not b = c DIV a, b, c a <- b…arrow_forward(Part B) Design 32KW, 16-way set associative unblocked cache that has 8 bytes per word. Assume a 64 bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the index field? (c) How many bits are used for the tag? (d) What is the physical size of each set (show as bits/row * # of rows, x * 2v)?arrow_forward(Part C) Design 32KW, fully associative cache that has 4 32-bit words per block. Assume a 32. bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the block offset? (c) How many bits are used for the index field? (d) How many bits are used for the tag? (e) What is the physical size of each set (show as bits/row * # of rows, x * 2V)?arrow_forwardPlease send me answer within 10 min!! I will rate you good for sure!! Please send me proper explanation!!arrow_forward(d) Given memory holes (i.e., unused memory blocks) of 100K, 500K, 200K, 300K and 600K (in address order) as shown below, how would each of the first-fit, next-fit, best- fit algorithms allocate memory requests of 120K, 320K, 280K, 90K and 210K (in this order). The shaded areas are used/allocated regions that are not available. 100k 500k 200k 300k 600k Figure 2: Current status of main memoryarrow_forwardComputer science Computer organization subjectarrow_forwardarrow_back_iosSEE MORE QUESTIONSarrow_forward_ios
Recommended textbooks for you
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education