Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
bartleby

Concept explainers

Question
Book Icon
Chapter 6, Problem 6.27HW

A)

Program Plan Intro

Given Information:

A 2-way associative cache is given.

For line-0:

SetIndexTagValidByte0Byte1Byte2Byte3
009186303F10
1451604FE023
2EB0----
3060----
4C71067807C5
57110BDE184B
6911A0B7262D
7460----

For line-1:

SetIndexTagValidByte0Byte1Byte2Byte3
0000----
138100BC0B37
20B0----
332112087BAD
40514067C23B
56E0----
6F00----
7DE112C08837

B)

Program Plan Intro

Given Information:

A 2-way associative cache is given.

For line-0:

SetIndexTagValidByte0Byte1Byte2Byte3
009186303F10
1451604FE023
2EB0----
3060----
4C71067807C5
57110BDE184B
6911A0B7262D
7460----

For line-1:

SetIndexTagValidByte0Byte1Byte2Byte3
0000----
138100BC0B37
20B0----
332112087BAD
40514067C23B
56E0----
6F00----
7DE112C08837

Blurred answer
Students have asked these similar questions
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal.                   Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Please do in correct way!
For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag  Index Offset 63-13 12-4 3-0 a.  What is the cache block size (in bytes)?b.  What is the cache size (in bytes)?c.  What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?d. For the same block and cache sizes, you want to implement a 4-way set-associative cache, what is the number of index bit and the number of tag bits?
Knowledge Booster
Background pattern image
Computer Science
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.
Similar questions
SEE MORE QUESTIONS
Recommended textbooks for you
  • Text book image
    Systems Architecture
    Computer Science
    ISBN:9781305080195
    Author:Stephen D. Burd
    Publisher:Cengage Learning
Text book image
Systems Architecture
Computer Science
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Cengage Learning