Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 6.1, Problem 6.5PP
A.
Program Plan Intro
Lifetime of SSD:
Intel guarantees about 128 petabytes or PB (
1 PB =
B.
Program Plan Intro
Lifetime of SSD:
Intel guarantees about 128 petabytes or PB (
1 PB =
C.
Program Plan Intro
Lifetime of SSD:
Intel guarantees about 128 petabytes or PB (
1 PB =
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Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- at least 190 ns? Q2. Develop a 64-bit wide memory interface that contains SRAM at locations (EEFE80000- EEFEFFFFF) H and EPROM at locations (FF2F00000-FF2FFFFFF) H for the Pentium II µp using 16L8 as a PLA decoder circuit. For the hypotheses 80xxx µp, if we decide to modify the bit wide memory to 32-bit, suggest the memory locations for both memory types and develop the memory interfacing circuit. If you know that, the required time for reading from any single EPROM chip is 950 ns and the up clocked at 15 MHz, how many wait states are require for doing that? Sketch the required circuit for generating the desired number of the wait states.arrow_forwardAnswer the following questions. A. A computer system has a main memory access time as 60ns. you as a computer organization expert has been asked to reduce the memory access time to 20ns by adding a suitable cache. Assume that the miss probability is 10%. What should be the fastness of cache (in terms of access time) for this requirement? B. Consider the instruction ADD R1, X, which adds the contents of location X from the contents of register R1, and places the result in R1. Show the micro-operations used during fetch and execution phase of the instruction.arrow_forwardConsider a demand-paging system with a paging disk that has an average access time of 20 milliseconds(ms). Addresses are translated through a page table in main memory, with an access time of 2millisecond (ms) per main memory access. Assume page fault ratio is 10 percent.(a) [5 pt] Assume the paper table has two levels. What’s the effective memory access time?(b) [5 pt] To improve this time, we can add a TLB that reduces access time if the page-table entry is inthe TLB. Assume access time to TLB is 0.5 millisecond (ms) and 80 percent of the accesses hit in the TLB.Assume page table has one level. What’s the effective memory access time?arrow_forward
- (Part D) Assuming an ALU with a basic CPI = 1, with NO cache, and a DRAM access time of 500 cycles. (a) What is the effective CPI? Note without a cache, every instruction has to come from DRAM. (b) Suppose we add an L1 cache to that with 1 cycle access and a miss rate of 10%? (c) Now suppose we add an L2 cache to that with 10 cycle access and a miss rate of 5%? (d) Now suppose we add an L3 cache to that with 100 cycle access and a miss rate of 1%? (e) Now suppose we add an L4 cache to that with 200 cycle access and a miss rate of %%? (f) Now suppose we add an L5 cache to that with 400 cycle access and a miss rate of % %arrow_forwardAs we have seen, a potential drawback of SSDs is that the underlying flash memory can wear out. For example, for the SSD in (Figure 1), Intel guarantees about 128 petabytes (128×1015128×1015 bytes) of writes before the drive wears out. Given this assumption, estimate the lifetime (in years) of this SSD for the following workloads: Average case: The SSD is written to at a rate of 20 GB/dayGB/day (the average daily write rate assumed by some computer manufacturers in their mobile computer workload simulations). Express your answer as an integer in years. The answer is not 17534 yearsarrow_forwardI need the answer as soon as possiblearrow_forward
- Consider a swapping system in which memory consists of the following hole sizes in memory order: 10 MB, 4 MB, 20 MB, 18 MB, 7 MB, 9 MB, 12 MB and 15 MB. Which hole is taken for successive segment requests of (i) 12 MB (ii) 10 MB (iii) 9 MB for first fit? Now repeat the question for best fit and worse fit.arrow_forward7arrow_forward) We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 200 ps 300 ps 150 ps 250 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu (i.e. add, sub,…) beq lw sw 45 % 20 % 20 % 15% a.) What is the clock cycle time in a pipelined and non-pipelined processor? b.) What is the total latency of seven LW instructions in a pipelined and non-pipelined processor (assume no stalls or hazards) c.) Assuming there are no stalls or hazards, what is the utilization of the data memory? (Hint) R-type instruction: IF ID EX MEM WB: no data memory access required beq: no data memory access required lw: IF ID EX MEM WB: data memory access required sw: IF ID EX MEM WB: data memory access required % of lw + % of sw = ?arrow_forward
- Problem: Consider a long sequence of accesses to a disk with an average seek time of 6 ms and an average rotational delay of 3 ms. The average size of a block being accessed is 8K bytes. The data transfer rate from the disk is 34 Mbytes/sec. (a) Assuming that the data blocks are randomly located on the disk, estimate the average percentage of the total time occupied by seek operations and rotational delays. (b) Repeat part (a) for the situation in which disk accesses are arranged so that in 90 percent of the cases, the next access will be to a data block on the same cylinder.arrow_forwardProblem 4. Consider a memory system with a cache and main memory. It takes 10ns to access the cache, and 100ns to access the main memory. If the effective (memory) access time is 10% greater that the cache access time, what is the hit ration H?arrow_forwardLast solution had mistakes For a 5,000 RPM disk, assume its average seek time is 7 msec, and it has 100 MB/sec bandwidth; assume the sector size is 512 bytes. (In this problem, MB means 1,000,000 bytes.) How long does it take to access 2,048 bytes of contiguous data on average? What is the average throughput (bytes per second) if the user accesses 512 bytes for each I/O? Assume the data is perfectly aligned on the disk. How long does it take to access 1 MB of contiguous data (on average)? What is the average throughput (bytes per second) if the user accesses 1 MB for each I/O operations? Assume the data is perfectly aligned on the disk. Suppose a user expects his or her average throughput to reach 50% of the disk’s maximum bandwidth. Find the minimum I/O size needed to achieve this.arrow_forward
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