Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Concept explainers
Question
Chapter 6.1, Problem 6.4PP
A.
Program Plan Intro
Given Information:
A 1 MB file consisting of 512 byte logical blocks is stored on a disk drive with the following characteristics:
| Parameter | Value |
| Rotational Rate | 10000 RPM |
| 5 ms | |
| Average numbers of sectors or tracks | 1000 |
| Surfaces | 4 |
| Sector size | 512 bytes |
B.
Program Plan Intro
Given Information:
A 1 MB file consisting of 512 byte logical blocks is stored on a disk drive with the following characteristics:
| Parameter | Value |
| Rotational Rate | 10000 RPM |
| 5 ms | |
| Average numbers of sectors or tracks | 1000 |
| Surfaces | 4 |
| Sector size | 512 bytes |
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solution
Students have asked these similar questions
1. External Memory
(a) Explain in terms of seek time, rotational delay, acces time, and transfer time, the magnetic disk
performance parameters and timing of a disk I/O transfer.
(b) Give a comparision between Hard Disk Drives (HDD) and Solid State Drives (SSD). Name two issues
related to SSDS that are not faced by HDDS and two issues related to HDDS that are not faced by
SSDS.
Question#4: Consider a file system that uses inodes to represent files. Disk blocks are 8 KB in size,
and a pointer to a disk block requires 4 bytes. This file system has 12 direct disk blocks, as well as
single, double, and triple indirect disk blocks. What is the maximum size of a file that can be stored in
this file system?
pls solve it pls dont say anymore uh-oh ı need solve of it
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
Knowledge Booster
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.Similar questions
- I need the answer as soon as possiblearrow_forwardOperating System: Consider a demand-paging system with a paging disk. The average disk access time is 10 milliseconds, and the average memory access time is 100 nanoseconds. Assume 0.1 percent of the access causes page faults. What is the effective memory access time? In order to achieve no more than 5 percent overhead due to demand paging for this system, what should the maximum page fault rate be?arrow_forwardd) Provide a block diagram of a register file that uses a 2-to-4 decoder to read from and write to the registers. This block diagram can be used to write a VHDL entity of this memory.arrow_forward
- a. Provide the four (4) memory allocation scheme of RAM b. Provide the three (3) deallocation alternative situationsarrow_forward8. Consider a disk pack with a seek titme of 4 milliseconds and rotational speed of 10000 rotalions per mitute (RPM) thas sects per track and each secton can store 512 bytes of data. Consider a file stored in the disk The ile contains 2000 sectors. Assume that every sector sccess necessitates a seck, and the average rotational latency for sccessing esch sector is half of the tine for on complete rotation The total time (in milliseconds) needed to read the entire file isarrow_forward7arrow_forward
- Problem D. DNA Input file: Output file: Time limit: standard input standard output 1 second 256 megabytes Memory limit: As you know desoxyribonucleic acid consists of 4 mucleobases: adenine, guanine, cytosine, thymine. This nucleobases must form pairs: adenine with thymine and guanine with cytosine. You are given the sequence of nucleobases in the first part of DNA spiral. Please, find its second part. Input You are given the only string DNA. It is guaranteed that DNA consists only of uppercase letters 'A', "C', T', 'G'. Output Print the second part of DNA spiral. Examples standard input standard output ACTG TGÁC A GTA СATarrow_forward4. A1 Kilobyte RAM has a word size of 16 bits,' (a) How many address bits does the RAM require? (b) How many D latches does the RAM require? (c) Draw a clearly labeled logic diagram of a binary storage cell and describ (d) Explain the concept of read and write for a memory unit. [arrow_forward3) What is the size of the memory for each case below? Each segment is All segments are • Overall memory is .... .... ......arrow_forward
- Problem 4.1 A memory system is needed in a new design to support a small amount of data storage outside of the processor. The design is to be based on the 16 K bit CY7C128A SRAM orga- nized as 2 K x 8. (a) Provide a high-level block diagram for such an interface. (b) Provide a high-level timing diagram for the interface to the SRAM from the microprocessor, assuming that separate address and data busses are available. Define any control signals that may be necessary. (c) Design the interface based on the timing diagram from part (a). (d) Analyze the memory performance for a write and a read operation of 1, 10, and 100 bytes.arrow_forwardI need it qcklyarrow_forward(c) The following Sigma 16 program has been loaded into memory at address 0000: load R3,y[RO] load R4,x[RO] lea R5, 2[RO] sub R1,R4,R3 mul R2,R1,R5 store R2,w[RO] trap RO,RO,RO x data 10 y data 12 w data 0 Show the content of the memory writing hexadecimal representation and using a table with 3 columns: the memory address, the contents of that memory address, and an explanation of what "the content (of that memory address) means". As a reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c. And here the opcodes for RX instructions: lea 0, load 1, store 2. [7]arrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
C++ for Engineers and ScientistsComputer ScienceISBN:9781133187844Author:Bronson, Gary J.Publisher:Course Technology Ptr
C++ for Engineers and Scientists
Computer Science
ISBN:9781133187844
Author:Bronson, Gary J.
Publisher:Course Technology Ptr