A)
Explanation of Solution
Cache entry and cache byte:
The program running on a machine references the 1-byte word at address “
First, one needs to convert the hexadecimal address into binary form:
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
B)
Explanation of Solution
Memory reference:
The address format (1 bit per box) for address “
CT | CT | CT | CT | CT | CT | CT | CT | CI | CI | CI | CO | CO |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
The memory reference for the above address format “
Want to see the full answer?
Check out a sample textbook solutionChapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
- Computer science Computer organization subjectarrow_forwardTopic : Writing MIPS code. 1.Consider the equation and write MIPS code for it: X=(A[4]+B[2])+(B[3]-5X); Assume array A stores floating-point values and its base address in $s0 and array B stores integer values and its base address is in $s1 register. X is in register $s2.arrow_forward1)Encode the binary data 1010101010 into an even parity Hamming code. 2)A direct mapped cache consists of 256 slots. Main memory contains 64K blocks of 16 words each. Access time of the cache is 15 ns, and that for the main memory is 120 ns. Assume that main memory is accessed in parallel with cache look up. Initially, the cache is empty. (a) Give the format of the memory address. (b) Compute the effective access time, if suppose the hit ratio for read is 90%.arrow_forward
- m ofessor, S. aw-Hill tion... V !!! ar textbook As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table Decimal 4669 2227 13916 34587 48870 12608 49225 hex 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 1 2 3 4 5 (a) For each access shown above, list 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4…arrow_forward5.barrow_forwardQuestion 3 (Cache Memory Mapping): I (a) For the main memory address 0:0:0, briefly explain how a search is performed in two-way set associative mapping. Assume that the main memory size is 4 GB, the cache memory is 8 KB and the size of cache block is 32 bytes. (b) A 4-way set associative mapped cache consists of 64 blocks, divided into 4 sets. Main memory consists of 4K blocks, each containing 128 locations. Complete the following format for the main memory address by showing all your workings and find the tag size. [Hint: Calculate the no. of locations in the main memory, which gives the memory size in terms of the total number of bits] , Set No. Block No. Location Within Block No. of bitsarrow_forward
- instruction is in the first picture cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0 : CB1 | CB2 | CB 3 | ... | CB N// Set 1 : CB1 | CB2 | CB 3 | ... | CB N// ...// Set M-1 : CB1 | CB2 | CB…arrow_forwardi need the answer of B only pleasearrow_forwardPlease solve Q) which is a valid offset pair? A) DS:DI C) ES:SI B) CS:SP D) SS:BP Q) The number of General Purpose Registers present in 8086 microprocessor? 6 10 34 4 Q) With 20-bit address lines memory size of microprocessor would be? Q) Calculate the physical address of the segment offset pair 7213:5686 77686H 0C899H 777B9H 777B6H Q) ALU of 8086 is 20 bit 8 bit 16 bit 32 bit Q) Memory size of 8086 microprocessor is 4KB 256 bytes 128bytes 1MB Q) In 8086 data access by which register uses SS as the default segment register? Both SP and BP SP Dl BP Q) Flag resister is None of the above 20 bit 16 bit 8 bit Q) The starting address of the segment is called None of the above Effective address Base address Offset address Q) Instruction queue size in 8086 is 4 bytes 4 bits 6 bytes 6 bits Q) MOV CX, [481d] ; assuming DS= 2162H, logical address will be: Q) AL= 53 CL=29 ADD AL, CL DAA What is the value of AL after…arrow_forward
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education