Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 6, Problem 6.28HW

This problem concerns the cache in Practice Problem 6.12.

  1. A.    List all of the hex memory addresses that will hit in set 2.
  2. B.     List all of the hex memory addresses that will hit in set 4.
  3. C.     List all of the hex memory addresses that will hit in Set 5.
  4. D.    List all of the hex memory addresses that will hit in set 7.
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Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S t
- A cache has been designed such that it has 1024 lines, with each line or block containing 8 words. Determine the line number, tag, and word position for the 20-bit address 3E9D216 using the direct mapping method.
Please do in correct way!
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