Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
Question
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Chapter 6, Problem 6.38HW

A)

Program Plan Intro

Given Information:

The given code is:

// define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[i][j].c=0;

square[i][j].m=0;

square[i][j].y=1;

square[i][j].k=0;

}

}

Write hit:

If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.

  • If the state of information is in valid state then it executes a write-through operation.
  • It then updates the memory and block and changes its blocked state to reserved state.

Write miss:

A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.

B)

Program Plan Intro

Given Information:

The given code is:

// define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[i][j].c=0;

square[i][j].m=0;

square[i][j].y=1;

square[i][j].k=0;

}

}

Write hit:

If the information in the cache is reserved or in dirty state then the cache line is updated in its place without updating memory set from its state to dirty.

  • If the state of information is in valid state then it executes a write-through operation.
  • It then updates the memory and block and changes its blocked state to reserved state.

Write miss:

A partial cache line write is handed as a read miss followed by a write hit. All the other caches are left in the invalid state and the reserved state is occupied by the current state.

C)

Program Plan Intro

Given Information:

The given code is:

//define structure

square point_color

{

// variable declaration

int c;

int m;

int y;

int k;

};

// declare structure array

struct point_color square[16][16];

int i,j;

// traverse through the array

for(i=0;i<16;i++)

{

//traverse through elements

for(j=0;j<16;j++)

{

//square all elements of the 2-D array

square[i][j].c=0;

square[i][j].m=0;

square[i][j].y=1;

square[i][j].k=0;

}

}

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I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?
HD Video C x 3ll al N X Ue G X ogle agi X Microsoft moodle.nct.edu.om/pluginfile.php/67858/mod_resource 100% 212 2. A singer voice is sampled for 4 second by an 8-bit ADC at a sampling frequency of 10 kHz. The samples are stored on a memory chip. What is the minimum memory size both in [bits and bytes] required to store all the samples? i. How long the signal must be sampled to store the samples in 100Mbytes CD- ROM iii. What should be the highest frequency component of the signal? iv.If sampling frequency is doubled then how long the signal must be sampled to store samples in 100Mbytes CD-ROM 14 Marks
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