Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 6.4, Problem 6.9PP

Explanation of Solution

Cache Addressing:

The primary storage hierarchy contains cache lines that are grouped into sets. If each set contains k lines then we say that the cache is k-way associative.

A data request has an address specifying the location of the requested data. Each cache-line sized chunk of data from the lower level can only be placed into one set. The set that it can be placed into depends on its address.

The number of cache sets is equal to the number of cache blocks divided by the number of ways of associativity.

Number of tag bits = (address _bit _length ) - (exponent _of_ index )  (exponent _of _offset)

The least significant bits are used to determine the block offset.

For example:

One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:

The Index (CI):

s=log2(S)   =log2(23) = 3 log2(2) = 3

The block off set (CO):

s = log2(B) = log2(22) = 2 log2(2) = 1

The tag bit (CT):

t = m - (s + b) = 13 - (3 + 2) = 13 - 5 = 8

Hence, the “2” lower bits are block offsets (CO); followed by 3 sets of bit index (CI) and the remaining bits are tag bits (CT).

The following table gives the parameters for a number of different caches and the number of cache sets(S), tag bits(t), set index bits (s) and block offset bits (b) are defined.

CachemCBEStsb
1321024412562282
232102484322453
3321024323212705

The values for the above table are described below:

For cache-1:

It is given that B=4,E=1, C=1024 and m=32.

Hence:

S=(cache_memory)/(B×E)=(1024)/(4×1)=256

s=log2(S)  =log2(256) = log2(28) = 8 log2(2) = 8

b =log2(B)=log2(4)=2

t = m - (s + b) = 32- (8 + 2) = 32-10 = 22

For cache-2:

It is given that B=8, E=4,C=1024 and m=32

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Students have asked these similar questions
(Part B) Design 32KW, 16-way set associative unblocked cache that has 8 bytes per word. Assume a 64 bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the index field? (c) How many bits are used for the tag? (d) What is the physical size of each set (show as bits/row * # of rows, x * 2v)?
Q3) A computer system has 1 Mbyte of main memory, 16 bytes block size, and 64 Kbytes cache memory. a. For the main memory addresses of CABBE, 01234, and, FO010 find tag, cache line address, and word offsets for a direct- mapped cache. b. Give any two main memory addresses with different tags that map to the same cache slot for direct-mapped cache.c. For the main memory addresses of CABBE and, FO010 find tag and word offset values for a fully-associative cache. d. For the main memory addresses of CABBE and, FO010 find tag, cache set, and word offset values for a two-way set- associative cache.
(Part C) Design 32KW, fully associative cache that has 4 32-bit words per block. Assume a 32. bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the block offset? (c) How many bits are used for the index field? (d) How many bits are used for the tag? (e) What is the physical size of each set (show as bits/row * # of rows, x * 2V)?
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