Explanation Introduction: The ROM is the type of memory in which the data can only be read and not be written. The ROM comes under the category of the volatile memory as they store the data even when the system is turned on, thus the data can be retained later. The seven segment array has seven LED that displays the decimal numbers from 0 to 9 the design for the segment is shown below. The required diagram is shown in Figure 1 Consider the row inputs are, W 1 , W 2 , W 3 ....... , W 8 , W 9 . The columns input are C 1 , C 2 , C 3 , C 4 ... C 7 and the outputs are Y D 1 , Y D 2 , Y D 3 , Y D 4 ..... Y D 7 . The column selected transistors are M 1 , M 2 , M 3 and M 4 is the column selected transistor. Case (i) When row 1 is to be addressed the output is row 0000 . To obtain this output the row and the column inputs are W 1 , C 1 , C 2 , C 3 , C 4 , C 5 and C 6 must be at logic 1. The transistors that are biased in the conduction state are M 00 , M 01 , M 02 , M 03 , M 04 and M 05 . Case (ii) When row 2 is to be addressed the output is row 0001 . To obtain this output the row and the column inputs are W 2 , C 2 and C 3 must be at logic 1. The transistors that are biased in the conduction state in row 2 are M 11 and M 12 . Case (iii) When row 3 is to be addressed the output is row 0010 . To obtain this output the row and the column inputs are W 3 , C 1 , C 2 , C 4 , C 5 and C 7 must be at logic 1

Microelectronics: Circuit Analysis and Design

4th Edition

ISBN: 9780073380643

Author: Donald A. Neamen

Publisher: McGraw-Hill Companies, The

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Chapter 16, Problem D16.95P

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To design: TheNMOS mask-programmed ROM that decodes a binary inputand produces the output for seven segment array.

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Chapter 16, Problem D16.94P

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Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS inverter with resistor load in...Ch. 16 - The enhancementload NMOS inverter in Figure...Ch. 16 - Prob. 16.3EP Ch. 16 - Prob. 16.4EP Ch. 16 - Consider the NMOS inverter with enhancement load,...Ch. 16 - Prob. 16.2TYU Ch. 16 - (a) Consider the results of Exercise Ex 16.1....Ch. 16 - Prob. 16.5EP Ch. 16 - Prob. 16.6EP Ch. 16 - (a) Design a threeinput NMOS NOR Logic gate with...

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To design: TheNMOS mask-programmed ROM that decodes a binary inputand produces the output for seven segment array.

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Chapter 16 Solutions