Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
bartleby

Concept explainers

bartleby

Videos

Question
Book Icon
Chapter 16, Problem 16.46P

(a)

To determine

The noise margins of a CMOS inverter biased at given value.

(a)

Expert Solution
Check Mark

Answer to Problem 16.46P

The value of NMH is 1.025V and NML is 1.025V .

Explanation of Solution

Calculation:

The expression to determine the value of the KN is given by,

  KN=kn2(WL)n

Substitute 100μA/V2 for kn and 2 for (WL)n in the above equation.

  KN=100μA/ V 22(2)=100μA/V2

The expression to determine the value of the KP is given by,

  KP=kp2(WL)p

Substitute 40μA/V2 for kp and 5 for (WL)p in the above equation.

  KP=40μA/ V 22(5)=100μA/V2

The expression to determine the value of the low level of the input voltage is given by,

  VIL=VTN+38(VDD+VTPVTN)

Substitute 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VIL=0.4V+38(3.3V+( 0.4V)0.4V)=1.3375V

The expression to determine the value of the high level of input voltage is given by,

  VIH=VTN+58(VDD+VTPVTN)

Substitute 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VIH=0.4V+58(3.3V+( 0.4V)0.4V)=1.9625V

The expression to determine the value of the high level of output voltage is given by,

  VOHU=12((1+ K n K p )VIL+VDD( K n K p )VTNVTP)

Substitute 1.3375V for VIL , 100μA/V2 for Kp , 100μA/V2 for Kn , 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VOHU=12( ( 1+ 100 μA/ V 2 100 μA/ V 2 )( 1.2716V )+2.5V( 100 μA/ V 2 50 μA/ V 2 )( 1.3375V ) ( 0.4V )+0.4[]V)=2.9875V

The expression to determine the value of the high level of output voltage is given by,

  VOLU=vIH(1+ K n K p )VDD( K n K p )VTNVTP2KnKp

Substitute 1.9625V for VIH , 100μA/V2 for Kp , 100μA/V2 for Kn , 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VOLU=( 1.9625V)( 100 μA/ V 2 100 μA/ V 2 )3.3V( 100 μA/ V 2 100 μA/ V 2 )04V( 0.4V)2( 100 μA/ V 2 100 μA/ V 2 )=0.3125V

The low level of the noise margin is given by,

  NML=VILVOLU

Substitute 1.3375V for VIL and 0.3125V for VOLU in the above equation.

  NML=1.3375V0.3125V=1.025V

The low level of the noise margin is given by,

  NMH=VOHUVIH

Substitute 1.9625V for VIH and 2.9875V for VOHU in the above equation.

  NMH=2.9875V1.9625V=1.025V

Conclusion:

Therefore, the value of NMH is 1.025V and NML is 1.025V .

(b)

To determine

The noise margins of a CMOS inverter biased at VDD

(b)

Expert Solution
Check Mark

Answer to Problem 16.46P

The value of s is 0.9413V and NML is 1.1112V .

Explanation of Solution

Calculation:

The expression to determine the value of the KN is given by,

  KN=kn2(WL)n

Substitute 100μA/V2 for kn and 4 for (WL)n in the above equation.

  KN=100μA/ V 22(2)=100μA/V2

The expression to determine the value of the KP is given by,

  KP=kp2(WL)p

Substitute 40μA/V2 for kp and 12 for (WL)p in the above equation.

  KP=40μA/ V 22(12)=240μA/V2

The expression to determine the value of the low level of the input voltage is given by,

  VIL=VTN+VDD+VTPVTN( K n K p 1)(2 K n K p K n K p +31)

Substitute 240μA/V2 for Kp , 200μA/V2 for Kn , 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VIL=0.4V+3.3V+( 0.4V)0.4V( 200 μA/ V 2 240 μA/ V 2 1)(2 200 μA/ V 2 240 μA/ V 2 200 μA/ V 2 240 μA/ V 2 +3 1)=1.4127V

The expression to determine the value of the high level of input voltage is given by,

  VIH=VTN+VDD+VTPVTN( K n K p 1)(2 K n K p 3 K n K p +11)

Substitute 240μA/V2 for Kp , 200μA/V2 for Kn , 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VIH=0.4V+3.3V+( 0.4V)0.4V( 200 μA/ V 2 240 μA/ V 2 1)( 2( 200 μA/ V 2 240 μA/ V 2 ) 3( 200 μA/ V 2 240 μA/ V 2 )+1 1)=2.0370V

The expression to determine the value of the high level of output voltage is given by,

  VOHU=12((1+ K n K p )VIL+VDD( K n K p )VTNVTP)

Substitute 1.4127V for VIL , 240μA/V2 for Kp , 200μA/V2 for Kn , 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VOHU=12(( 1+ 200 μA/ V 2 240 μA/ V 2 )( 1.4127V)+3.3V( 200 μA/ V 2 240 μA/ V 2 )( 0.4V)( 0.4V))=2.9783V

The expression to determine the value of the high level of output voltage is given by,

  VOLU=vIH(1+ K n K p )VDD( K n K p )VTNVTP2KnKp

Substitute 2.0370V for VIH , 240μA/V2 for Kp , 200μA/V2 for Kn , 0.4V for VTN , 0.4V for VTP and 3.3V for VDD in the above equation.

  VOLU=2.0370V( 1+ 200 μA/ V 2 240 μA/ V 2 )3.3V( 200 μA/ V 2 240 μA/ V 2 )( 0.4V)( 0.4V)2( 200 μA/ V 2 240 μA/ V 2 )=0.3007V

The low level of the noise margin is given by,

  NML=VILVOLU

Substitute 1.4127V for VIL and 0.3007V for VOLU in the above equation.

  NML=1.4127V0.3007V=1.1112V

The low level of the noise margin is given by,

  NMH=VOHUVIH

Substitute 2.0370V for VIH and 2.9783V for VOHU in the above equation.

  NMH=2.9783V2.0370V=0.9413V

Conclusion:

Therefore, the value of NMH is 0.9413V and NML is 1.1112V .

Want to see more full solutions like this?

Subscribe now to access step-by-step solutions to millions of textbook problems written by subject matter experts!
Students have asked these similar questions
5) What are the noise margins for a symmetrical CMOS inverter operating with VDD = 3.3 V and VrN = -VTP = 0.75 V? (b) Repeat for a CMOS inverter having (W |L)n = (W/L)p operating with VdD = 3.3 V and Vrn = –VTP = 0.75 V.
A full bridge inverter with RLC load having the following values: R=7.5 Ohms, L-12.5 mH, C-22 uF. The switching frequency is 500 Hz and the DC input voltage is 180V. The average current supply (consider up to the fifth harmonics in calculation) would be equal to: Select one: a. None of these b. 3.84A C. 1.64A d. 5.74A
Problem Three A particular digital inverter is operated with a supply voltage of 1.2V. The small signal voltage gain is desired to be 50 V/V. Unlike an ideal inverter Vm is desired to be 0.4 of the supply voltage. Assume the following parameter values: VOL = 0V and VoH = VDD a) Determine the corresponding values for VL and VH. b) Determine the noise margins of the inverter. c) Calculate the large signal gain defined as: Ay = (VoH– VoL) / (VH- VIL). %3D

Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
Knowledge Booster
Background pattern image
Electrical Engineering
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, electrical-engineering and related others by exploring similar questions and additional content below.
Similar questions
SEE MORE QUESTIONS
Recommended textbooks for you
Text book image
Introductory Circuit Analysis (13th Edition)
Electrical Engineering
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:PEARSON
Text book image
Delmar's Standard Textbook Of Electricity
Electrical Engineering
ISBN:9781337900348
Author:Stephen L. Herman
Publisher:Cengage Learning
Text book image
Programmable Logic Controllers
Electrical Engineering
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education
Text book image
Fundamentals of Electric Circuits
Electrical Engineering
ISBN:9780078028229
Author:Charles K Alexander, Matthew Sadiku
Publisher:McGraw-Hill Education
Text book image
Electric Circuits. (11th Edition)
Electrical Engineering
ISBN:9780134746968
Author:James W. Nilsson, Susan Riedel
Publisher:PEARSON
Text book image
Engineering Electromagnetics
Electrical Engineering
ISBN:9780078028151
Author:Hayt, William H. (william Hart), Jr, BUCK, John A.
Publisher:Mcgraw-hill Education,
NMOS vs PMOS and Enhancement vs Depletion Mode MOSFETs | Intermediate Electronics; Author: CircuitBread;https://www.youtube.com/watch?v=kY-ka0PriaE;License: Standard Youtube License