Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.99P

(a)

To determine

The maximum allowed tolerance in the R1

(a)

Expert Solution
Check Mark

Answer to Problem 16.99P

The maximum allowed value of the tolerance is 5.88% .

Explanation of Solution

Calculation:

The given diagram is shown in Figure 1

  Microelectronics: Circuit Analysis and Design, Chapter 16, Problem 16.99P

The expression to determine the analog output voltage vO when the resistor R1 is connected to the reference voltage is given by,

  vO=(b12+b24+b38+b416)(VR)

Substitute 5V for VR , 1 for b1 , 0 for b2 , 0 for b3 and 0 for b4 in the above equation.

  vO=(12+04+08+0 16)(( 5V))=2.5V

The expression to determine the value of the least significant digit is given by,

  LSB=VR2n

Substitute 5V for VR and 4 for n in the above equation.

  LSB=5V24=0.3125V

The expression to determine the value of the output analog voltage with maximum error is given by,

  vO(max)=vO±12LSB

Substitute 2.5V for vO and 0.3125V for LSB in the above equation.

  vO( max)=(2.5V)±12(0.3125V)=2.34375V,2.65625V \

The expression to determine the value of the output analog voltage with maximum error (vO( max)) in terms of the maximum allowable tolerance in the resistance R1 from the circuit is given by,

  vO(max)=(RFR1+ΔR1)(VR)

Substitute 10kΩ for RF , 20kΩ for R1 and 5V for VR in the above equation.

  vO( max)=( 10kΩ 20kΩ+Δ R 1 )(( 5V))ΔR1=( 10kΩ v O( max ) )(5V)20kΩ   ...... (1)

Substitute 2.34375V for vO(max) in the above equation.

  ΔR1=( 10kΩ 2.34375V)(5V)20kΩ=1.333kΩ

The expression to determine the percentage allowed tolerance in the value of resistance R1 in terms of percentage %ΔR1 is given by,

  %ΔR1=(ΔR1R1)100   ...... (2)

Substitute 1.333kΩ for ΔR1 and 20kΩ for R1 in the above equation.

  %ΔR1=( 1.333kΩ 20kΩ)100=6.7%

Substitute 2.65625V for vO(max) in equation (1)

  ΔR1=( 10kΩ 2.65625V)(5V)20kΩ=|1.1765kΩ|=1.1765kΩ

Substitute 1.1765kΩ for ΔR1 and 20kΩ for R1 in equation (2)

  %ΔR1=( 1.1765kΩ 20kΩ)100=5.88%

Conclusion:

Therefore, the maximum allowed value of the tolerance is 5.88% .

(b)

To determine

The maximum allowed tolerance in the value of R4

(b)

Expert Solution
Check Mark

Answer to Problem 16.99P

The maximum allowed value of the tolerance is 33.3% .

Explanation of Solution

Calculation:

The expression to determine the analog output voltage vO when the resistor R4 is connected to the reference voltage is given by,

  vO=(b12+b24+b38+b416)(VR)

Substitute 5V for VR , 0 for b1 , 0 for b2 , 0 for b3 and 1 for b4 in the above equation.

  vO=(02+04+08+1 16)(( 5V))=0.3125V

The expression to determine the value of the output analog voltage with maximum error is given by,

  vO(max)=vO±12LSB

Substitute 0.3125V for vO and 0.3125V for LSB in the above equation.

  vO( max)=(0.3125V)±12(0.3125V)=0.15625V,0.46875V

The expression to determine the value of the output analog voltage with maximum error (vO( max)) in terms of the maximum allowable tolerance in the resistance R4 from the circuit is given by,

  vO(max)=(RFR4+ΔR4)(VR)

Substitute 10kΩ for RF , 160kΩ for R4 and 5V for VR in the above equation.

  vO( max)=( 10kΩ 160kΩ+Δ R 4 )(( 5V))ΔR4=( 10kΩ v O( max ) )(5V)160kΩ   ...... (3)

Substitute 0.15625V for vO(max) in the above equation.

  ΔR4=( 10kΩ 0.15625V)(5V)160kΩ=160kΩ

The expression to determine the percentage allowed tolerance in the value of resistance R4 in terms of percentage %ΔR4 is given by,

  %ΔR4=(ΔR4R4)100   ...... (4)

Substitute 160kΩ for ΔR4 and 160kΩ for R4 in the above equation. ΔR4

  %ΔR4=( 160kΩ 160kΩ)100=100%

Substitute 0.46875V for vO(max) in equation (1)

  ΔR4=( 10kΩ 0.46875V)(5V)160kΩ=|53.3334kΩ|=53.3334kΩ

Substitute 53.3334kΩ for ΔR4 and 160kΩ for R4 in equation (2)

  %ΔR4=( 53.3334kΩ 160kΩ)100=33.3%

Conclusion:

Therefore, the maximum allowed value of the tolerance is 33.3% .

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Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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