Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Question
Chapter 16, Problem 16.88P
(a)
To determine
The width to length ratio of the driver transistor.
(b)
To determine
The value of the standby cell current and the total memory power dissipation for a standby voltage.
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Students have asked these similar questions
Suppose you have 8 LED's connected to port-B (Bo-B7) of PIC16F877A and one switch
connected to port-D (Do) as shown in figure below. Write a program code that performs a
nibble (4-bits) toggling: if the switch is released then LED's (Bo to B3) are OFF and LED's
(B4 to B7) are ON, while if the switch is pressed then LED's (Bo to B3) are ON and LED's
(B4 to B7) are OFF. Use 300ms delay for each case with 4MHz frequency.
13
14
22 NATHON 20
U1
OSC1/CLKIN
U2
33
REOINT
20
34
OSC2/CLKOUT
19
RB1
35
3
18
RB2
RADIANO debt0RB3PGM
30
4
17
37
5
10
RA1/AN1
RB4
38
RA2/ANZ/VREF-/CVREF
15
RB5
39097
RA3/AN3VREF RB6/PGC
7
14
40
RA4/TOCK/C1OUT
13
RB7/PGO
RAS/ANA/SS/CZOUT
15
RCO/T1OSO/TICKI
10
11
REQIANS/RD
18
RC1/T10S/CCP2
17
10
RE1/AN/WR
REZ/ANTICS
MCLR/Vpp/THV
RC2/CCP1
LED-BARGRAPH-RED
RC3/SCK/SCL
RC4/SDUSDA
RC5/SDO
Eng of ROSTX/CX
RC7/RX/DT
RDO/PSPO
RD1/PSP1
RD2PSP2
RO3/PSP3
RD4/PSP4
ROS/PSP5
RD6/PSP6
RD7/PSP7
PIC16F877A
+5V
R1
100R
Write a PIC16F877A program that flash ON the 8-LED's connected to port-B by using
two switches connected to port-D (Do & D₁) as shown in figure below, according to the
following scenarios: (Hint: Use 500ms delay for each case with 4MHz frequency)
1. When Do=1 then B₁,B3,B, are ON.
2. When Do 0 then Bo,B2,B4, B5, B6 are ON.
3. When D₁=1 then B4,B,,B6,B7 are ON.
4. When D₁-0 then Bo,B1,B2,B3 are ON.
U1
5
33
OSC/CLION
OSC2/CLKOUT
ROOINT
RB1
35
RB2
20
17
RACIANO
RESPOM
RATANT
RAZIANZ/VREF-CVREF
RBS
RA3/AN3/VREF+
REPOC
39
14
40
RA4/TOCK C1OUT
13
RB7/PGO
12
RASIAN/SCOUT
15
ROOT1050/TICK
+5V
REGIANERD
REVANDVIR
REZANTICS
RCMT10SUCCP2
17
RC2/CCP1
LED-BARGRAPH-RED
RC3SCHISCL
23
---
MCUANTV
RC4/SOSDA 24
RCS/SDO
RCB/TICK
RC7/RXDT
25
ROOPSPO
RDMPSP1
RD2PSF2
RO3PSP3
RD4PSP4
RDSPSPS
PIC16F877A
ROOPSP
RO7/PSP7
R2
R1
100R 100R
Question 5
The following data were obtained from testing a 48-kVA 240/4800 V step up transformer.
Open-circuit test
Short-circuit test
Voltage (V)
240
150
Current (I)
2
10
Power (W)
120
600
Determine the equivalent circuit of the transformer as viewed from the primary side.
Ans: Rc = 480 ohm, Xm = 123.94 ohm, Reqp = 0.015 ohm, Xeqp = 0.034 ohm
Chapter 16 Solutions
Microelectronics: Circuit Analysis and Design
Ch. 16 - Consider the NMOS inverter with resistor load in...Ch. 16 - The enhancementload NMOS inverter in Figure...Ch. 16 - Prob. 16.3EPCh. 16 - Prob. 16.4EPCh. 16 - Consider the NMOS inverter with enhancement load,...Ch. 16 - Prob. 16.2TYUCh. 16 - (a) Consider the results of Exercise Ex 16.1....Ch. 16 - Prob. 16.5EPCh. 16 - Prob. 16.6EPCh. 16 - (a) Design a threeinput NMOS NOR Logic gate with...
Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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