Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.37P

(a)

To determine

The peak current in the inverter during the switching cycle.

(a)

Expert Solution
Check Mark

Answer to Problem 16.37P

The value of the current in the transistor is 24.2μA .

Explanation of Solution

Calculation:

The expression to determine the value of the KN is given by,

  KN=kn2(WL)n

Substitute 80μA/V2 for kn and 2 for (WL)n in the above equation.

  KN=80μA/ V 22(2)=80μA/V2

The expression to determine the value of the KP is given by,

  KP=kp2(WL)p

Substitute 40μA/V2 for kp and 4 for (WL)p in the above equation.

  KP=40μA/ V 22(4)=80μA/V2

The expression to determine the transition points VIt is given by,

  VIt=VDD+VTP+ K N K P VTN1+ K N K P

Substitute 1.8V for VDD , 0.35V for VTP , 80μA/V2 for KP and 80μA/V2 for KN and 0.35V for VTN in the above equation.

  VIt=1.8V+( 0.35V)+ 80 μA/ V 2 80 μA/ V 2 ( 0.35V)1+ 80 μA/ V 2 80 μA/ V 2 =0.9V

The expression for the maximum value of the current through the NMOS transistor is given by,

  iD,max=KN(vIV TN)2

Substitute 80μA/V2 for KN , 0.35 for VTN and VIt for VI in the above equation.

  iD,max=80μA/V2(V It0.35V)2

Substitute 0.9V for VIt in the above equation.

  iD,max=80μA/V2(0.9V0.35V)2=24.2μA

Conclusion:

Therefore, the value of the current in the transistor is 24.2μA .

(b)

To determine

The peak current in the inverter during the switching cycle.

(b)

Expert Solution
Check Mark

Answer to Problem 16.37P

The maximum value of the current in the transistor is 29.34μA .

Explanation of Solution

Calculation:

The expression to determine the value of the KN is given by,

  KN=kn2(WL)n

Substitute 80μA/V2 for kn and 2 for (WL)n in the above equation.

  KN=80μA/ V 22(2)=80μA/V2

The expression to determine the value of the KP is given by,

  KP=kp2(WL)p

Substitute 40μA/V2 for kp and 6 for (WL)p in the above equation.

  KP=40μA/ V 22(6)=120μA/V2

The expression to determine the transition points VIt is given by,

  VIt=VDD+VTP+ K N K P VTN1+ K N K P VTN

Substitute 1.8V for VDD , 0.35V for VTP , 120μA/V2 for KP and 80μA/V2 for KN and 0.35V for VTN in the above equation.

  VIt=1.8V+( 0.35V)+ 80 μA/ V 2 120 μA/ V 2 ( 0.35V)1+ 80 μA/ V 2 120 μA/ V 2 =0.95561V

The expression for the maximum value of the current through the NMOS transistor is given by,

  iD,max=KN(vIV TN)2

Substitute 80μA/V2 for KN , 0.35 for VTN and VIt for VI in the above equation.

  iD,max=80μA/V2(V It0.35V)2

Substitute 0.95561V for VIt in the above equation.

  iD,max=80μA/V2(0.95561V0.35V)2=29.34μA

Conclusion:

Therefore, the maximum value of the current in the transistor is 29.34μA .

(c)

To determine

The peak current in the inverter during the switching cycle.

(c)

Expert Solution
Check Mark

Answer to Problem 16.37P

The maximum value of the current in the transistor is 33.22μA .

Explanation of Solution

Calculation:

The expression to determine the value of the KN is given by,

  KN=kn2(WL)n

Substitute 80μA/V2 for kn and 4 for (WL)n in the above equation.

  KN=80μA/ V 22(4)=160μA/V2

The expression to determine the value of the KP is given by,

  KP=kp2(WL)p

Substitute 40μA/V2 for kp and 4 for (WL)p in the above equation.

  KP=40μA/ V 22(4)=80μA/V2

The expression to determine the transition points VIt is given by,

  VIt=VDD+VTP+ K N K P VTN1+ K N K P VTN

Substitute 1.8V for VDD , 0.35V for VTP , 80μA/V2 for KP and 160μA/V2 for KN and 0.35V for VTN in the above equation.

  VIt=1.8V+( 0.35V)+ 160 μA/ V 2 80 μA/ V 2 ( 0.35V)1+ 160 μA/ V 2 80 μA/ V 2 =0.8056V

The expression for the maximum value of the current through the NMOS transistor is given by,

  iD,max=KN(vIV TN)2

Substitute 80μA/V2 for KN , 0.35 for VTN and VIt for VI in the above equation.

  iD,max=80μA/V2(V It0.35V)2

Substitute 0.8056V for VIt in the above equation.

  iD,max=80μA/V2(0.8056V0.35V)2=33.22μA

Conclusion:

Therefore, the maximum value of the current in the transistor is 33.22μA .

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Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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