Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.36P

(a)

To determine

To plot: The graph of current in the transistor as a function of the input voltage for given range.

(a)

Expert Solution
Check Mark

Answer to Problem 16.36P

The required plot is shown in Figure 2

Explanation of Solution

Calculation:

The given diagram is shown in Figure 1.

  Microelectronics: Circuit Analysis and Design, Chapter 16, Problem 16.36P , additional homework tip  1

Consider the case when the input voltage is equal to zero.

The NMOS device is in the cutoff region the drain current of the transistor is zero and when the PMOS transistor is in the non-saturation region its drain current is also zero.

Consider the case when 0vIVDD2 .

The PMOS transistor in the Non-saturation and the NMOS just started to conduct and then enter in the saturation mode.

The expression for the drain current of the NMOS transistor is given by,

  iDN=KN(vIV TN)2

The expression for the drain current of the PMOS transistor is given by,

  iDP=KP(vIV TN)2

The CMOS drain current is due to the drain current of the NMOS alone and is given by,

  iD=iDN

Substitute KN(vIV TN)2 for iDN in the above equation.

  iD=KN(vIV TN)2

Substitute 120μA/V2 for KN and 0.4V for VTN in the above equation.

  iD=120μA/V2(vI0.4V)2

The tale to determine the value of the output current for the different value of the output voltage is shown below.

The required table is shown in Table 1

Table 1

    vI(V)iD(μA)A
    0.51.26
    0.65.04
    0.820.1
    0.931.5
    1.161.74
    1.2591.25

Consider the case when the input voltage is VDD2vIVDD+VTP , in this case the NMOS is in non-saturation and the PMOS is in saturation.

The expression for the drain current of the PMOS in saturation is given by,

  iDP=KP(V DDvI+V TP)2

The expression for the drain current of the NMOS in non-saturation is given by,

  iDN=KN(2(vIV TN)vO( v O )2)

The CMOS current depends only on the current through the drain current of the PMOS and is given by,

  iD=iDP

Substitute KP(V DDvI+V TP)2 for iDP in the above equation.

  iD=KP(V DDvI+V TP)2

Substitute 2.5V for VDD , 120μA/V2 for KN and 0.6V for VTP in the above equation.

  iD=120μA/V2(2.5V+6.63× 10 34JsvI0.6V)2

The table for the output current for the different values of the input voltage is shown below.

The required table is shown in Table 2

Table 2

    vI(V)iD(μA)A
    1.343.2
    1.430
    1.525
    1.610
    1.81.2
    1.90

Consider the case when the input voltage is given by,

  VDD+VTPvIVDD

For the above case the NMOS is in non-saturation region and the drain current is zero. The PMOS is in cut off and the drain current zero as the circuit is open.

The drain current when the input voltage is zero and the circuit is opened is given by,

  iD=0

The plot for the CMOS drain current against the input voltage from the values of table 1 and table 2 is shown below.

The required plot is shown in Figure 2

  Microelectronics: Circuit Analysis and Design, Chapter 16, Problem 16.36P , additional homework tip  2

Conclusion:

Therefore, the required plot is shown in Figure 2.

(b)

To determine

To plot: The current in the transistor as a function fo the input voltage.

(b)

Expert Solution
Check Mark

Answer to Problem 16.36P

The required plot is shown in Figure 3

Explanation of Solution

Calculation:

Consider the case when the voltage VDD is 1.8V .

Consider the input voltage as 0vIVTN , for this case the NMOS is in cutoff the drain current is zero for both the transistor, thus the PMOS is in non-saturation.

Consider the case when the input voltage is VTNvIVDD2 .

The expression for the drain current of the NMOS is given by,

  iDN=KN(vIV TN)2

The expression for the drain current of the PMOS transistor is given by,

  iDP=KP(2(V DDvI+V TP)(V DDvO)( V DD v O )2)

The CMOS drain current is due to the drain current of the NMOS alone and is given by,

  iD=iDN

Substitute KN(vIV TN)2 for iDN in the above equation.

  iD=KN(vIV TN)2

Substitute 120μA/V2 for KN and 0.4V for VTN in the above equation.

  iD=120μA/V2(vI0.4V)2

The table for the output current for the different values of the input voltage is shown below.

The required table is shown in Table 3

Table 3

    vI(V)iD(μA)A
    0.51.26
    0.65.04
    0.820.1
    0.931.5

Consider the case when the input voltage vI is VDD2<vI>VDD+VTP .

The PMOS transistor is in the non-saturation and the NMOS just beings to conduct and then goes to saturation.

The expression for the drain current of the NMOS is given by,

  iDN=KN(2( v I V TN )vOvO2)2

The expression for the drain current of the PMOS transistor is given by,

  iDP=KP(V DDvI+V TP)2

The CMOS drain current is due to the drain current of the PMOS alone and is given by,

  iD=iDP

Substitute KP(V DDvI+V TP)2 for iDP in the above equation.

  iD=KP(V DDvI+V TP)2

Substitute 1.8V for VDD , 120μA/V2 for KP and 0.6V for VTN in the above equation.

  iD=120μA/V2(1.8VvI0.6V)2

The table for the output current for the different values of the input voltage is shown below.

The required table is shown in Table 4

Table 4

    vI(V)iD(μA)A
    0.957.5
    14.8
    1.11.2
    1.20

Consider the case when the input voltage is VDD+VTPvI>VDD the NMOS is in non-saturation, and the value of the drain current is zero, the PMOS is in cut off. Thus, the drain current of the CMOS is in cut off and the circuit is opened.

The plot between the drain current and the input voltage from table 3 and table 4 is shown below.

The required plot is shown in Figure 3

  Microelectronics: Circuit Analysis and Design, Chapter 16, Problem 16.36P , additional homework tip  3

Conclusion:

Therefore, the required plot is shown in Figure 3

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Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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