Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.43P

(a)

To determine

To show: The resistance of the NMOS device is equal to 1[( k n ( W L ) n)( V DD V TN)] when vI0 and resistance of PMOS is 1[( k P ( W L ) P)( V DD V TP)] .

(a)

Expert Solution
Check Mark

Explanation of Solution

Calculation:

Consider the case when the input voltage is,

  vI=VDD

The expression for the conduction parameter of the NMOS transistor is given by,

  KN=( k n2)(WL)n

The expression for the drain current of the NMOS transistor when the transistor is biased in the non-saturation is given by,

  iDN=KN[2(vIVTN)vDSNvDSN2]

The expression to determine the resistance of the NMOS transistor is given by,

  1rds=diNdvDSN

Substitute KN[2(vIVTN)vDSNvDSN2] for iDN in the above equation.

  1r ds=d( K N [ 2( v I V TN ) v DSN v DSN 2 ])dv DSN1r ds=2KN(vIV TN)KNVDSNrds=12KN( v I V TN )KNV DSN

Substitute 0V for vDSN , ( k n2)(WL)n for KN and VDD for vI in the above equation.

  rds=12( k n 2 ) ( W L )n( V DD V TN )( k n 2 ) ( W L )n( 0V)=1 k n ( W L )n( V DD V TN )

The expression for the current in the NMOS transistor is given by,

  iDP=KP[2(vI+VTP)vSDP( v SDP)2]

The expression for the conduction parameter of the NMOS transistor is given by,

  KP=( k p2)(WL)p

The expression for the resistance of the PMOS device is given by,

  1rSD=diDPdvSDP

Substitute KP[2(vI+VTP)vSDP( v SDP)2] for iDP in the above equation.

  1r SD=ddv SDP[KP[2( v I + V TP )v SDP ( v SDP )2]]rSD=12KP( v I + V TP )2KPv SDP

Substitute KP[2(vI+VTP)vSDP( v SDP)2] for iDP in the above equation.

  rSD=12KP(vI+V TP)vSDP2KPvSDP

Substitute ( k p2)(WL)p for KP , VDD for vI and 0 for vSDP in the above equation.

  rSD=12( k p 2 ) ( W L )p( V DD + V TP )(0)2( k p 2 ) ( W L )p(0)=1[( k P ( W L ) P )( V DD + V TP )]

Conclusion:

Therefore, the resistance of the NMOS device is 1kn( W L )n(V DDV TN) and PMOS transistor is 1[( k P ( W L ) P)( V DD+ V TP)] .

(b)

To determine

The value of the maximum current that the NMOS transistor can sink and the current that the PMOS can source.

(b)

Expert Solution
Check Mark

Answer to Problem 16.43P

The maximum value of the current of that NMOS device can sink is 0.336mA and the current that it can source is 0.336mA and the maximum current that PMOS can source is 0.168mA .S

Explanation of Solution

Calculation:

The expression for the resistance off the NMOS transistor is given by,

  rds=1kn( W L )n(V DDV TN)

Substitute 80μA/V2 for kn , 2 for (WL)n , 5V for VDD and 0.8V for VTN in the above equation.

  rds=180μA/ V 2(2)( 5V0.8V)=1.488×103MΩ

The conversion from 1MΩ into kΩ is given by,

  1MΩ=103kΩ

The conversion from 1.488×103MΩ into kΩ is given by,

  1.488×103MΩ=1.488kΩ

The conversion from 2.9761×103MΩ into kΩ is given by,

  2.9761×103MΩ=2.9761kΩ

The expression to determine the value of the current through the NMOS is given by,

  iDN(max)=vDSNrDS

Substitute 0.5V for vDSN and 1.488kΩ for rDS in the above equation.

  iDN(max)=0.5V1.488kΩ=0.336mA

The expression for the resistance of the PMOS transistor is given by,

  rSD=1[( k P ( W L ) P)( V DD+ V TP)]

Substitute 2 for (WL)P , 40μA/V2 for kP , 5V for VDD and 0.8V for VTP in the above equation.

  rSD=1[( 40 μA/ V 2 )( 2)( 5V+( 0.8V ))]=2.9761×103MΩ=2.9761kΩ

The expression for the maximum value of the current through the PMOS transistor is given by,

  iDP(max)=vDSPrSD

Substitute 0.5V for vDSP and 2.9761kΩ for rDS in the above equation.

  iDP(max)=0.5V2.9761kΩ=0.168mA

Conclusion:

Therefore, the maximum value of the current of that NMOS device can sink is 0.336mA and the current that it can source is 0.336mA and the maximum current that PMOS can source is 0.168mA .

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Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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