Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Textbook Question
Chapter 10, Problem 10.2P
The matched transistors
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Students have asked these similar questions
Create the PLC ladder logic diagram
for the logic gate circuit displayed in
Figure 7-35. The pilot light red (PLTR)
output section has three inputs: PBR,
PBG, and SW. Pushbutton red (PBR)
and pushbutton green (PBG) are inputs
to an XOR logic gate. The output of the
XOR logic gate and the inverted switch
SW) are inputs to a two-input AND
logic gate. These inputs generate the
pilot light red (PLTR) output.
The two-input AND logic gate output
is also fed into a two-input NAND logic
PBR
PBG
SW
TSW
PLTR
Figure 7-35. Logic gate circuit for Example 7-3.
PLTW
Goodheart-Willcox Publisher
gate. The temperature switch (TSW) is the other input to the NAND logic gate. The output generated from
the NAND logic gate is labeled pilot light white (PLTW).
Imaginary Axis (seconds)
1
6. Root locus for a closed-loop system with L(s) =
is shown below.
s(s+4)(s+6)
15
10-
0.89
0.95
0.988
0.988
-10
0.95
-15
-25
0.89
20
Root Locus
0.81
0.7
0.56
0.38
0.2
5
10
15
System: sys
Gain: 239
Pole: -0.00417 +4.89
Damping: 0.000854
Overshoot (%): 99.7
Frequency (rad/s): 4.89
System: sys
Gain: 16.9
Pole: -1.57
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 1.57
0.81
0.7
0.56
0.38
0.2
-20
-15
-10
-5
5
10
Real Axis (seconds)
From the values shown in the figure, compute the following.
a) Range of K for which the closed-loop system is stable.
b) Range of K for which the closed-loop step response will not have any overshoot.
Note that when all poles are real, the step response has no overshoot.
c) Smallest possible peak time of the system. Note that peak time is the smallest
when wa is the largest for the dominant pole.
d) Smallest possible settling time of the system. Note that peak time is the smallest
when σ is the largest for the dominant pole.
For a band-rejection filter, the response drops below this half power point at two locations as visualised in Figure 7, we need to find these
frequencies. Let's call the lower frequency-3dB point as fr and the higher frequency -3dB point fH. We can then find out the bandwidth as
f=fHfL, as illustrated in Figure 7.
0dB
Af
-3 dB
Figure 7. Band reject filter response diagram
Considering your AC simulation frequency response and referring to Figure 7, measure the following from your AC simulation. 1% accuracy:
(a) Upper-3db Frequency (fH) =
Hz
(b) Lower-3db Frequency (fL) =
Hz
(c) Bandwidth (Aƒ) =
Hz
(d) Quality Factor (Q) =
Chapter 10 Solutions
Microelectronics: Circuit Analysis and Design
Ch. 10 - The circuit parameters for the two-transistor...Ch. 10 - Consider the circuit shown in Figure 10.3. The...Ch. 10 - The parameters of the circuit shown in Figure 10.5...Ch. 10 - Consider the Widlar current source in Figure 10.9....Ch. 10 - Consider the circuit in Figure 10.10. Assume the...Ch. 10 - A Widlar current source is shown in Figure 10.9....Ch. 10 - Figure 10.12 shows the N-output current mirror....Ch. 10 - Prob. 10.1TYUCh. 10 - Prob. 10.2TYUCh. 10 - For the Wilson current source in Figure 10.8, the...
Ch. 10 - Prob. 10.4TYUCh. 10 - Prob. 10.8EPCh. 10 - Prob. 10.9EPCh. 10 - Consider the JFET circuit in Figure 10.24. The...Ch. 10 - Consider Design Example 10.8. Assume transistor...Ch. 10 - The bias voltages of the MOSFET current source in...Ch. 10 - Prob. 10.7TYUCh. 10 - All transistors in the MOSFET modified Wilson...Ch. 10 - A simple BJT amplifier with active load is shown...Ch. 10 - Prob. 10.9TYUCh. 10 - Prob. 10.10TYUCh. 10 - Prob. 10.11TYUCh. 10 - Prob. 10.12EPCh. 10 - For the circuit in Figure 10.40(a), the transistor...Ch. 10 - Prob. 10.12TYUCh. 10 - Repeat Example 10.12 for the case where a resistor...Ch. 10 - Prob. 10.14TYUCh. 10 - Prob. 1RQCh. 10 - Explain the significance of the output resistance...Ch. 10 - Prob. 3RQCh. 10 - Prob. 4RQCh. 10 - What is the primary advantage of a BJT cascode...Ch. 10 - Prob. 6RQCh. 10 - Can a piecewise linear model of the transistor be...Ch. 10 - Prob. 8RQCh. 10 - Sketch the basic MOSFET two-transistor current...Ch. 10 - Discuss the effect of mismatched transistors on...Ch. 10 - Prob. 11RQCh. 10 - Sketch a MOSFET cascode current source circuit and...Ch. 10 - Discuss the operation of an active load.Ch. 10 - What is the primary advantage of using an active...Ch. 10 - Prob. 15RQCh. 10 - What is the impedance seen looking into a simple...Ch. 10 - What is the advantage of using a cascode active...Ch. 10 - Prob. 10.1PCh. 10 - The matched transistors Q1 and Q2 in Figure...Ch. 10 - Prob. 10.3PCh. 10 - Reconsider the circuit in Figure 10.2(a). Let...Ch. 10 - Prob. 10.5PCh. 10 - The transistor and circuit parameters for the...Ch. 10 - The bias voltages in the circuit shown in Figure...Ch. 10 - Consider the current source in Figure 10.2(b). The...Ch. 10 - Prob. 10.9PCh. 10 - Prob. 10.10PCh. 10 - Prob. D10.11PCh. 10 - In the circuit in Figure P10.11, the transistor...Ch. 10 - Prob. D10.13PCh. 10 - Consider the circuit shown in Figure P 10.14. The...Ch. 10 - Design a basic two-transistor current...Ch. 10 - The values of for the transistors in Figure P10.16...Ch. 10 - Consider the circuit in Figure P10.17. The...Ch. 10 - All transistors in the N output current mirror in...Ch. 10 - Design a pnp version of the basic three-transistor...Ch. 10 - Prob. D10.20PCh. 10 - Consider the Wilson current source in Figure...Ch. 10 - Consider the circuit in Figure P10.22. The...Ch. 10 - Consider the Wilson current-source circuit shown...Ch. 10 - Consider the Widlar current source shown in Figure...Ch. 10 - Prob. 10.25PCh. 10 - Consider the circuit in Figure P10.26. Neglect...Ch. 10 - (a) For the Widlar current source shown in Figure...Ch. 10 - Consider the Widlar current source in Problem...Ch. 10 - (a) Design the Widlar current source such that...Ch. 10 - Design a Widlar current source to provide a bias...Ch. 10 - Design the Widlar current source shown in Figure...Ch. 10 - The circuit parameters of the Widlar current...Ch. 10 - Consider the Widlar current source in Figure 10.9....Ch. 10 - Consider the circuit in Figure P10.34. The...Ch. 10 - The modified Widlar current-source circuit shown...Ch. 10 - Consider the circuit in Figure P10.36. Neglect...Ch. 10 - Consider the Widlar current-source circuit with...Ch. 10 - Assume that all transistors in the circuit in...Ch. 10 - In the circuit in Figure P10.39, the transistor...Ch. 10 - Consider the circuit in Figure P10.39, with...Ch. 10 - Consider the circuit shown in Figure P10.41....Ch. 10 - For the circuit shown in Figure P 10.42, assume...Ch. 10 - Consider the circuit in Figure P10.43. The...Ch. 10 - Consider the MOSFET current-source circuit in...Ch. 10 - The MOSFET current-source circuit in Figure P10.44...Ch. 10 - Consider the basic two-transistor NMOS current...Ch. 10 - Prob. 10.47PCh. 10 - Consider the circuit shown in Figure P10.48. Let...Ch. 10 - Prob. 10.49PCh. 10 - The circuit parameters for the circuit shown in...Ch. 10 - Prob. 10.51PCh. 10 - Figure P10.52 is a PMOS version of the...Ch. 10 - The circuit shown in Figure P10.52 is biased at...Ch. 10 - The transistor circuit shown in Figure P10.54 is...Ch. 10 - Assume the circuit shown in Figure P10.54 is...Ch. 10 - The circuit in Figure P 10.56 is a PMOS version of...Ch. 10 - The transistors in Figure P10.56 have the same...Ch. 10 - Consider the NMOS cascode current source in Figure...Ch. 10 - Consider the NMOS current source in Figure P10.59....Ch. 10 - Prob. 10.60PCh. 10 - The transistors in the circuit shown in Figure...Ch. 10 - A Wilson current mirror is shown in Figure...Ch. 10 - Repeat Problem 10.62 for the modified Wilson...Ch. 10 - Prob. 10.64PCh. 10 - Prob. 10.65PCh. 10 - Prob. D10.66PCh. 10 - Prob. D10.67PCh. 10 - The parameters of the transistors in the circuit...Ch. 10 - Prob. 10.69PCh. 10 - Consider the circuit shown in Figure P10.70. The...Ch. 10 - Prob. 10.71PCh. 10 - Prob. D10.72PCh. 10 - Prob. 10.73PCh. 10 - Prob. D10.74PCh. 10 - Prob. 10.75PCh. 10 - For the circuit shown in Figure P10.76, the...Ch. 10 - Prob. 10.77PCh. 10 - Prob. 10.78PCh. 10 - The bias voltage of the MOSFET amplifier with...Ch. 10 - Prob. 10.80PCh. 10 - Prob. 10.81PCh. 10 - Prob. 10.82PCh. 10 - A BJT amplifier with active load is shown in...Ch. 10 - Prob. 10.84PCh. 10 - Prob. 10.85PCh. 10 - Prob. 10.86PCh. 10 - The parameters of the transistors in Figure P10.87...Ch. 10 - The parameters of the transistors in Figure P10.88...Ch. 10 - A BJT cascode amplifier with a cascode active load...Ch. 10 - Design a bipolar cascode amplifier with a cascode...Ch. 10 - Design a MOSFET cascode amplifier with a cascode...Ch. 10 - Design a generalized Widlar current source (Figure...Ch. 10 - The current source to be designed has the general...Ch. 10 - Designa PMOS version of the current source circuit...Ch. 10 - Consider Exercise TYU 10.10. Redesign the circuit...
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- P 4.4-21 Determine the values of the node voltages V1, V2, and v3 for the circuit shown in Figure P 4.4-21. 29 ww 12 V +51 Aia ww 22. +21 ΖΩ www ΖΩ w +371 ①1 1 Aarrow_forward1. What is the theoretical attenuation of the output voltage at the resonant frequency? Answer to within 1%, or enter 0, or infinity (as “inf”) Attenuation =arrow_forwardWhat is the settling time for your output signal (BRF_OUT)? For this question, We define the settling time as the period of time it has taken for the output to settle into a steady state - ie when your oscillation first decays (aka reduces) to less than approximately 1/20 (5%) of the initial value. (a) Settling time = 22 μs Your last answer was interpreted as follows: Incorrect answer. Check 22 222 What is the peak to peak output voltage (BRF_OUT pp) at the steady state condition? You may need to use the zoom function to perform this calculation. Select a time point that is two times the settling time you answered in the question above. Answer to within 10% accuracy. (a) BRF_OUT pp= mVpp As you may have noticed, the output voltage amplitude is a tiny fraction of the input voltage, i.e. it has been significantly attenuated. Calculate the attenuation (decibels = dB) in the output signal as compared to the input based on the formula given below. Answer to within 1% accuracy.…arrow_forward
- my previous answers for a,b,d were wrong a = 1050 b = 950 d=9.99 c was the only correct value i got previously c = 100hz is correctarrow_forwardV₁(t) ww ZRI ZLI ZL2 ZTH Zci VTH Zc21 Figure 8. Circuit diagram showing calculation approach for VTH and Z TH we want to create a blackbox for the red region, we want to use the same input signal conditions as previously the design of your interference ector circuit: Sine wave with a 1 Vpp, with a frequency of 100 kHz (interference) Square wave with 2.4Vpp, with a frequency of 10 kHz (signal) member an AC Thevenin equivalent is only valid at one frequency. We have chosen to calculate the Thevenin equivalent circuit (and therefore the ackbox) at the interference frequency (i.e. 100 kHz), and the signal frequency (i.e. 10 kHz) as these are the key frequencies to analyse. Your boss is assured you that the waveform converter module has been pre-optimised to the DAB Receiver if you use the recommended circuit topology.arrow_forwardVs(t) + v(t) + vi(t) ZR ZL Figure 1: Second order RLC circuit Zc + ve(t) You are requested to design the circuit shown in Figure 1. The circuit is assumed to be operating at its resonant frequency when it is fed by a sinusoidal voltage source Vs (t) = 2sin(le6t). To help design your circuit you have been given the value of inductive reactance ZL = j1000. Assume that the amplitude of the current at resonance is Is (t) = 2 mA. Based on this information, answer the following to help design your circuit. Use cartesian notation for your answers, where required.arrow_forward
- What is the attenuation at the resonant frequency? You should use the LTSpice cursors for your measurement. Answer to within 1% accuracy, or enter 0, or infinity (as "inf") (a) Attenuation (dB) = dB Check You may have noticed that it was significantly easier to use frequency-domain "AC" simulation to measure the attenuation, compared to the steps we performed in the last few questions. (i.e. via a time-domain "transient" simulation). AC analysis allows us to observe and quantify large scale positive or negative changes in a signal of interest across a wide range of different frequencies. From the response you will notice that only frequencies that are relatively close to 100 kHz have been attenuated. This is the result of the Band-reject filter you have designed, and shows the 'rejection' (aka attenuation) of any frequencies that lie in a given band. The obvious follow-up question is how do we define this band? We use a quantity known as the bandwidth. A commonly used measurement for…arrow_forwardV₁(t) ww ZRI ZLI ZL2 ZTH Zci VTH Zc21 Figure 8. Circuit diagram showing calculation approach for VTH and Z TH we want to create a blackbox for the red region, we want to use the same input signal conditions as previously the design of your interference ector circuit: Sine wave with a 1 Vpp, with a frequency of 100 kHz (interference) Square wave with 2.4Vpp, with a frequency of 10 kHz (signal) member an AC Thevenin equivalent is only valid at one frequency. We have chosen to calculate the Thevenin equivalent circuit (and therefore the ackbox) at the interference frequency (i.e. 100 kHz), and the signal frequency (i.e. 10 kHz) as these are the key frequencies to analyse. Your boss is assured you that the waveform converter module has been pre-optimised to the DAB Receiver if you use the recommended circuit topology.arrow_forwardVs(t) + v(t) + vi(t) ZR ZL Figure 1: Second order RLC circuit Zc + ve(t) You are requested to design the circuit shown in Figure 1. The circuit is assumed to be operating at its resonant frequency when it is fed by a sinusoidal voltage source Vs (t) = 2sin(le6t). To help design your circuit you have been given the value of inductive reactance ZL = j1000. Assume that the amplitude of the current at resonance is Is (t) = 2 mA. Based on this information, answer the following to help design your circuit. Use cartesian notation for your answers, where required.arrow_forward
- For a band-rejection filter, the response drops below this half power point at two locations as visualised in Figure 7, we need to find these frequencies. Let's call the lower frequency-3dB point as fr and the higher frequency -3dB point fH. We can then find out the bandwidth as f=fHfL, as illustrated in Figure 7. 0dB Af -3 dB Figure 7. Band reject filter response diagram Considering your AC simulation frequency response and referring to Figure 7, measure the following from your AC simulation. 1% accuracy: (a) Upper-3db Frequency (fH) = Hz (b) Lower-3db Frequency (fL) = Hz (c) Bandwidth (Aƒ) = Hz (d) Quality Factor (Q) =arrow_forwardV₁(t) ww ZRI ZLI Z12 Zci Zcz Figure 4. Notch filter circuit topology ши Consider the second order resonant circuit shown in Figure 4. Impedances ZLIZ C1. ZL2. Z c2 combine together forming a two-stage "band- reject" filter, so called because it rejects a "band" (aka range) of frequencies. This circuit topology is also commonly referred to as a "band-stop" filter or "notch" filter. The output of the DAB receiver block has been approximated via Thevenin's theorem for you as a voltage source Vs (t) and associated series impedance Z RI To succeed in our goal, we are going to use an iterative design approach. First we will design the interference rejector, and then repeat the process, using the output of the interference rejector to check the provided waveform converter works as intended.arrow_forward1. What is the settling time for your output signal (BRF_OUT)? For this question, We define the settling time as the period of time it has taken for the output to settle into a steady state - ie when your oscillation first decays (aka reduces) to less than approximately 1/20 (5%) of the initial value. (a) Settling timearrow_forward
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