A low dropout regulator (LDO) employs a PMOS pass transistor with an input reference voltage Vref = 1.2 V, minimum input supply Vin = 2.5 V before dropout and output voltage of Vout = 2 V. Assume transistor parameters of k' = 50 μA/V and threshold voltage Vtp = -0.7 V Determine the width to length ratio (WIL) of the PMOS for a maximum current load of 10 mA. Calculate the feedback amplifier gain required for a low frequency Power Supply Rejection (PSR) of 20 dB.
A low dropout regulator (LDO) employs a PMOS pass transistor with an input reference voltage Vref = 1.2 V, minimum input supply Vin = 2.5 V before dropout and output voltage of Vout = 2 V. Assume transistor parameters of k' = 50 μA/V and threshold voltage Vtp = -0.7 V Determine the width to length ratio (WIL) of the PMOS for a maximum current load of 10 mA. Calculate the feedback amplifier gain required for a low frequency Power Supply Rejection (PSR) of 20 dB.
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Transcribed Image Text:A low dropout regulator (LDO) employs a PMOS pass transistor with
an input reference voltage Vref = 1.2 V, minimum input supply Vin = 2.5
V before dropout and output voltage of Vout = 2 V. Assume transistor
parameters of k' = 50 μA/V and threshold voltage Vtp = -0.7 V
Determine the width to length ratio (WIL) of the PMOS for a
maximum current load of 10 mA.
Calculate the feedback amplifier gain required for a low
frequency Power Supply Rejection (PSR) of 20 dB.
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