Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPS resulting from this structural hazard by reordering code (reordering the instructions)? 3. Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPS to the code. Can you do the same with this structural hazard? If so. explain how. If not, explain why not. 4-1f we run the code above on a single-cycle computer, what kind of hazards are there?

Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPS resulting from this structural hazard by reordering code (reordering the instructions)? 3. Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPS to the code. Can you do the same with this structural hazard? If so. explain how. If not, explain why not. 4-1f we run the code above on a single-cycle computer, what kind of hazards are there?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Warn- do not copy from others
For the following assembly code that is vaguely MIPS-like, trace itsexecution in both the R3000 and R4000 pipelines using a Gantt chart (ortable of some kind).LOAD R1, Memory(12340)LOAD R2, Memory(12350)ADD R3, R1, R2 // R3 = R1 + R2ADD R3, R3, R3 // R3 = R3 + R3STORE R3, Memory(12360)
Consider the following assembly code: Instruction Description LOAD R1, M1 Read data from memory address M1 and store in R1. XOR R2, R1, R1 Logical Ex-OR between contents of R1 with R1 and store result in R2 BNEZ R2, Target1 Jump to Target if R2 is non-Zero ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 AND R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 Targetl: BEZ R2, Target2 Jump to Target if R2 is Zero LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 Save contents of R10 to memory address M4 END
5. Pipelined datapath has five stages, ie., instruction fetch (IF), decode (ID), execution (EX), memory (MEM), and write back (WB). It has a hazard detection unit. An instruction will be stalled at the decode stage if any of its operands isn't ready. Consider executing the following code on this datapath (1) At the end of fifth cycle of execution, what instruction will be in each of the pipeline stages? (If there is any "bubble" in the pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format. instruction IF instruction lw $r2, 10($1) sub $r4, $13, Sr2 add $r5, Sr6, $7 and Sr8, Sr4,$r5 IF ID EX (2) If the datapath has a forwarding unit to resolve the data hazard, what instruction will be in each of the pipeline stages at the end of the fifth cycle? (If there is any "bubble" in the -pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format: (D MEM EX WB.…
one Mil Q#1: Consider the instruction: add $2, $1, $3 What registers will be written and what registers will be read to execute this instruction? Registers to be written Registers to be read Q#2: Since we only support the add instruction, we don't care much for opcodes and funct codes and shamts. Therefore, suppose our programs are given to the processor as three inputs RD, RS, and RT. Each instruction executes within 1 clock periods Translate the following program to the RW, RS, RT inputs (in binary). clock period RD RS 1 2 3 4 RS RT Program add $2, $1, $3 add $0, $0, $1 add $1, $2, $2 add $1, $1, $1 Q#3: Design the single-cycle cessor datapath (only ID, EX and WB stages) using the mong different components. following datapath components.rly s the number of bits to be transferred in each data line and data bus connectio RD cik Registers RA RB RW BusA RegWrite Bus8 Bus W ALU zero ALU result overflow RT ALUOP
i need the answer quickly
We wish to execute a single LC-3 instruction that will subtract the decimal number 33 from R1 and put the result in R2. Can we do it? a. No, because the smallest number that fits 5 bits is -32b. No, because we don't have SUB instruction to subtractc. No, because the smallest number that fits 5 bits is -16d. Yes, we can do it with a single instruction.e. none of the above.
Orthogonality means that an instruction set has a "backup" instruction that can be used instead of any other instruction that gets the same result. You have to prove or disprove my assumption.
CPI stands for clock cycles per instruction. Speedup from pipelining = (Number of pipeline stages) / (Achieved CPI ). Assume a 5-stage pipeline. Assume that CPI = 1 when there are no pipeline stalls (the ideal case). Now assume that every branch instruction causes a 3 clock cycle stall in the pipeline. Assume that for the program being executed 30% of executed instructions are branch instructions. What speedup from pipelining is achieved by this program?
1. writing assembler Write assembly code that implements the following C code fragment. This is not a func- tion, so you should ignore function setup/teardown. You should assume that a is stored at 8(%rbp), b is stored in %edx, and c is stored at -4(%rbp). if (a && b> 0) C = b+4; (Remember that a is true if it is not 0, false if it is 0.)
Assume the initial value for X1 is is 11 and X2 is 22. Suppose we execute the code below on a version of the pipeline from your textbook that does not handle data hazards (i.e., the programmer handles data hazards by inserting NOP instructions where necessary). What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. ADDI X1,X2,#5 ADD X3,X1,X2 ADDI X4,X1,#15 ADD X5,X1,X1
Consider the following sequence of outcomes for a particular branch instruction: T, NT, T, NT, T, NT, T, NT…. Assume this sequence repeats indefinitely. Part A: The Easy Part What is the long-term (steady-state) accuracy of the predict-taken predictor? What about predict-not-taken? Part B: 1-bit predictor What is the long-term (steady-state) accuracy of the 1-bit predictor? If its initial state matters, explain. Part C: 2-bit predictor What is the long-term (steady-state) accuracy of the 2-bit predictor? If its initial state matters, explain. Part D: Custom Predictor Design your own predictor that uses no more than 2 bits of state to maximize prediction accuracy for this pattern. Show the state diagram, and give the long-term accuracy of your predictor. If its initial state matters, explain.