we would like to keep the pipeline full as much as possible and improve the performance. can we reorder the instructions to avoid NOPs? if so how?

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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we would like to keep the pipeline full as much as possible and improve the performance. can we reorder the instructions to avoid NOPs? if so how?

M
LOA!
PC
1
4
Address
>Add
Instruction
memory
1w R15, 0(R2)
add R14, R15, R15
1w
R16, 4(R2)
add R17, R16, R16
IF/ID
Instruction
Read
register 1
Read
register 2
Write
register
Write
data
Registers Read
data 2
Read
data 1
16
Sign-
extend
32
ID/EX
Shift
left 2
Q: Where does
add need R15?
Add Add
result
add
needs
R15
Zero
ALU ALU
result
M
A: No! Data is ready
at the END of the
MEM cycle, we need
it at the start of EXE
cycle for ADD!
Q: Can we
forward from
MEM?
Iw
has R15
Address
rite
Data
memory
Read
data
。Mux
Transcribed Image Text:M LOA! PC 1 4 Address >Add Instruction memory 1w R15, 0(R2) add R14, R15, R15 1w R16, 4(R2) add R17, R16, R16 IF/ID Instruction Read register 1 Read register 2 Write register Write data Registers Read data 2 Read data 1 16 Sign- extend 32 ID/EX Shift left 2 Q: Where does add need R15? Add Add result add needs R15 Zero ALU ALU result M A: No! Data is ready at the END of the MEM cycle, we need it at the start of EXE cycle for ADD! Q: Can we forward from MEM? Iw has R15 Address rite Data memory Read data 。Mux
The code below was written without regard for the delay slots.
(There may be NOPs missing. The pipeline has a double-pumped register file and forwarding.)
lw R15, 0(R2)
add
1w R16, 4(R2)
add R17, R16, R16
R14, R15, R15
Transcribed Image Text:The code below was written without regard for the delay slots. (There may be NOPs missing. The pipeline has a double-pumped register file and forwarding.) lw R15, 0(R2) add 1w R16, 4(R2) add R17, R16, R16 R14, R15, R15
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