When we execute a program that contains a lot of if-statements or for/while-loops, the pipeline of Teletraan-2 faces a problem. The instruction fetch stage does not know which branch of the if-statement shall be fetched, until the write back stage writes the True/False value of the ifcondition to a flag register. What should we do to alleviate the problem? A. Don't wait. Let the CPU predict which branch will probably be executed, and fetch the instruction(s) of that branch. If it is later revealed the prediction is wrong, undo the instruction(s). B. Don't wait. Fetch-decode-execute the instructions of all branches of the if-statement. C. Nothing. We can only let the instruction fetch stage wait for the write back stage to finish writing the value of the if-condition. D. Eliminate all if-statements during the assembly process.
When we execute a
of Teletraan-2 faces a problem. The instruction fetch stage does not know which branch of the
if-statement shall be fetched, until the write back stage writes the True/False value of the ifcondition to a flag register. What should we do to alleviate the problem?
A. Don't wait. Let the CPU predict which branch will probably be executed, and fetch the
instruction(s) of that branch. If it is later revealed the prediction is wrong, undo the
instruction(s).
B. Don't wait. Fetch-decode-execute the instructions of all branches of the if-statement.
C. Nothing. We can only let the instruction fetch stage wait for the write back stage to finish
writing the value of the if-condition.
D. Eliminate all if-statements during the assembly process.
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