Add control states to the following to implement a bitwise-OR-with-immediate instruction (as decoded by the when below), such that ori $rt,$rs,immed yields rt=(rs|immed). This is actually a MIPS instruction, as we'll discuss later. Hint: except for using bitwise OR instead of addition, it's essentially the same as the addi that is already handled by: when (op()) {addi} Addi when (op()) {ori} Ori Start: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */ Addi: SELrs, REGout, Yin IRimmedout, ALUadd, Zin Zout, SELrt, REGin, JUMP(Start) Ori: You can test your specification using the http://super.ece.engr.uky.edu:8088/cgi-bin/simple.cgiLinks to an external site. simulator. For testing, you can add the initial conditions: MEM[0]={ori}+rs(9)+rt(10)+immed(3) MEM[4]=0 $9=5 Register $10 should end-up holding the value 0x00000007 (3|5 = 7 decimal).
Add control states to the following to implement a bitwise-OR-with-immediate instruction (as decoded by the when below), such that ori $rt,$rs,immed yields rt=(rs|immed). This is actually a MIPS instruction, as we'll discuss later. Hint: except for using bitwise OR instead of addition, it's essentially the same as the addi that is already handled by:
when (op()) {addi} Addi
when (op()) {ori} Ori
Start:
PCout, MARin, MEMread, Yin
CONST(4), ALUadd, Zin, UNTILmfc
MDRout, IRin
Zout, PCin, JUMPonop
HALT /* Should end here on undecoded op */
Addi:
SELrs, REGout, Yin
IRimmedout, ALUadd, Zin
Zout, SELrt, REGin, JUMP(Start)
Ori:
You can test your specification using the http://super.ece.engr.uky.edu:8088/cgi-bin/simple.cgiLinks to an external site. simulator. For testing, you can add the initial conditions:
MEM[0]={ori}+rs(9)+rt(10)+immed(3)
MEM[4]=0
$9=5
Register $10 should end-up holding the value 0x00000007 (3|5 = 7 decimal).
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