Fill in the pipeline diagram for the following code fragment (instructions L1:L4) executed in a 5-stage pipeline with stages Fetch(F), Decode/Read Register (D), Execute (E), Memory (M), and Writeback Register (W). You may use the symbol S for pipeline stalls. The entries for Instruction L1 are already filled in. Complete the entries for Instructions for L2:L4.

Fill in the pipeline diagram for the following code fragment (instructions L1:L4) executed in a 5-stage pipeline with stages Fetch(F), Decode/Read Register (D), Execute (E), Memory (M), and Writeback Register (W). You may use the symbol S for pipeline stalls. The entries for Instruction L1 are already filled in. Complete the entries for Instructions for L2:L4.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

An 'instruction fetch/read' results in three sets of numbers that go to the Registers Block as studied in class. These three numbers in the instruction represent bits 25-21 for 'Read Register 1', bits 20-16 for 'Read Register 2', and bits 15-11 for the 'Write Register'. What does the 5 bits width of each of these indicate? a. That the word is 15 bits long in this architecture b. That each word is 32 bits long c. That there are 32 registers that can be addressed in this architecture d. That there are 15 registers that can be addressed in this architecture
Suppose the opcode of an MIPS instruction is 8 in decimal, and the rest of the machine code is 309FC88 in hexadecimal (from high-order bit to low-order bit). What is the instruction? When showing the registers, use names (e.g. $t0, $s2) instead of indices (e.g $8, $17). For branch instructions, show offset in place of label, e.g. beq $t1, $t2, 92. Answer:
Convert the given hex value to its R-format MIPS instruction by completing the following table. The instruction and letters for registers must be in lower case. DO NOT TYPE DOLLAR SIGNS WITH REGISTERS. Hex Opcode (decimal) rs (decimal) rt (decimal) rd (decimal) funct (decimal) Instruction 02488822 O 18 16 17 34 sub s4 $$1 " $ to " LA
Assume all of Pep/9's main memory is filled up with unary instructions. How many steps are there in each one? B) If there are no unary instructions, how many instructions can fit in the main memory? An equal number of unary and nonunary instructions are stored in the main memory. What is the total number of instructions?
In this case, every instruction receives its own data, independent of how the data for other instructions is obtained. We make advantage of a: A Multiple Data/Instruction B Multiple Iterations of Data or Instruction C Singular Data Single Inst D Singe Inst Multiple
Assume that the instruction pointer, EIP, contains 9810 and the assembly language representation of the instruction in memory at address 9810 is JAE 131. If the flags are currently CF=1, ZF=0 and SF=0 what is the value of the EIP after the instruction executes? The answer 102 is not correct so what is the correct answer?
From above question, if a branch instruction is a conditional branch instruction, the branch need not be taken; if the branch is not taken, the following instructions can be overlapped. When 80% of all branch instructions are conditional branch instructions, and 50% of the conditional branch instructions are such that the branch is taken, what is the average instruction execution time?
The description of three-address instructions species the components of each type of instruction, but it does not specify the representation of these instructions in a data structure. Write the three – address code for the following expressions:(i) a = b * −c + b * −C(ii) A = −B * (C + D)(iii) (4 * 7 + 1) * 2(iv) a * - (b + c)
The execution of an instructions includes the following stages : instruction fetch, instruction decode, register fetch, ALU operation, memory operation, and write back. The analysis is based on an implementation of the datapath and control unit of a 32-bit MIPS microarchitecture.
Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.
Suppose the opcode of an MIPS instruction is 9 in decimal, and the rest of the machine code is 1F67875 in hexadecimal (from high-order bit to low-order bit). What is the instruction? When showing the registers, use names (e.g. $t0, $s2) instead of indices (e.g $8, $17). For branch instructions, show offset in place of label, e.g. beq $t1, $t2, 92.
Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?