Fill in the pipeline diagram for the following code fragment (instructions L1:L4) executed in a 5-stage pipeline with stages Fetch(F), Decode/Read Register (D), Execute (E), Memory (M), and Writeback Register (W). You may use the symbol S for pipeline stalls. The entries for Instruction L1 are already filled in. Complete the entries for Instructions for L2:L4.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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Fill in the pipeline diagram for the following code fragment (instructions L1:L4)
executed in a 5-stage pipeline with stages Fetch(F), Decode/Read Register (D),
Execute (E), Memory (M), and Writeback Register (W). You may use the symbol S for
pipeline stalls. The entries for Instruction L1 are already filled in. Complete the entries
for Instructions for L2:L4.
L1
L2
L3
L4
L1: R1 R2 + R3
L2: R2 = MEM[R4]
L3: R4 = R1 + R3
L4: MEM[R5] = R3
C1
F
C2 C3
D
E
C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
M W
Transcribed Image Text:Fill in the pipeline diagram for the following code fragment (instructions L1:L4) executed in a 5-stage pipeline with stages Fetch(F), Decode/Read Register (D), Execute (E), Memory (M), and Writeback Register (W). You may use the symbol S for pipeline stalls. The entries for Instruction L1 are already filled in. Complete the entries for Instructions for L2:L4. L1 L2 L3 L4 L1: R1 R2 + R3 L2: R2 = MEM[R4] L3: R4 = R1 + R3 L4: MEM[R5] = R3 C1 F C2 C3 D E C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 M W
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