Z EXT Trap Vector MARMUX ADDR ADDER 2 E A2MUX F A1MUX The Complete LC-3 Data Path A PC PCMUX +1 D B DST REGISTER FILE SRC2 SRC1 G H
Z EXT Trap Vector MARMUX ADDR ADDER 2 E A2MUX F A1MUX The Complete LC-3 Data Path A PC PCMUX +1 D B DST REGISTER FILE SRC2 SRC1 G H
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
Using the diagram, what would be the paths.
![Z EXT
Trap
Vector
Legend:
MARMUX
A2MUX
SEXT
ADDR ADDER
2
E
S EXT
L
PC
Offset Offset
C
IR
F
D Incremented PC
E Address Adder 2
A1MUX
A Program Counter (PC)
B Destination Register
C Address Adder
The Complete LC-3 Data Path
S EXT
In
Immediate
NZP
MDR
M
CC LOGIC
I
I
1
I
1
I
I
I
1
1
I
|
MEMORY
ARRAY
A
PC
PCMUX
F Address Adder 1
G Source Register 2
H Source Register 1
ALU 2
JALU 1
I
CONTROL
UNIT
I |
|
FINITE
STATE
MACHINE
MAR
N
II
1
L
I
+1
-
¶
I
■
I
INPUTS
B
REGISTER
FILE
S2MUX
O
SRC2 SRC1
G
H
DST
2
ALU
K
1
OUTPUTS
K Arithmetic/Logic Unit (ALU)
L Instruction Register (IR)
M Memory Data Register (MDR)
N Memory Address Register (MAR)
O Memory Array](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fde8838b1-cf39-4d84-b3b3-badc79cd3854%2Faa080cba-0fee-4019-9466-317772149e1d%2Fypa09sf_processed.png&w=3840&q=75)
Transcribed Image Text:Z EXT
Trap
Vector
Legend:
MARMUX
A2MUX
SEXT
ADDR ADDER
2
E
S EXT
L
PC
Offset Offset
C
IR
F
D Incremented PC
E Address Adder 2
A1MUX
A Program Counter (PC)
B Destination Register
C Address Adder
The Complete LC-3 Data Path
S EXT
In
Immediate
NZP
MDR
M
CC LOGIC
I
I
1
I
1
I
I
I
1
1
I
|
MEMORY
ARRAY
A
PC
PCMUX
F Address Adder 1
G Source Register 2
H Source Register 1
ALU 2
JALU 1
I
CONTROL
UNIT
I |
|
FINITE
STATE
MACHINE
MAR
N
II
1
L
I
+1
-
¶
I
■
I
INPUTS
B
REGISTER
FILE
S2MUX
O
SRC2 SRC1
G
H
DST
2
ALU
K
1
OUTPUTS
K Arithmetic/Logic Unit (ALU)
L Instruction Register (IR)
M Memory Data Register (MDR)
N Memory Address Register (MAR)
O Memory Array
![For the instruction (0x6479, select all data paths that are used from the beginning of the
Decode Instruction phase through the end of the Store Result phase.
FYI: Be certain; Canvas deducts points for incorrect choices.
N to O
L to I
H to J
M to B
O to M
A to F
K to N
L to E
H to L
C to N
M to N
H to F](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fde8838b1-cf39-4d84-b3b3-badc79cd3854%2Faa080cba-0fee-4019-9466-317772149e1d%2Fsul16hv_processed.png&w=3840&q=75)
Transcribed Image Text:For the instruction (0x6479, select all data paths that are used from the beginning of the
Decode Instruction phase through the end of the Store Result phase.
FYI: Be certain; Canvas deducts points for incorrect choices.
N to O
L to I
H to J
M to B
O to M
A to F
K to N
L to E
H to L
C to N
M to N
H to F
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