Q1. Refer to the datapath design on slide no. 26 in Chapter 4 (part 1). While explaining this datapath, we did not discuss instructions that does immediate arithmetic, such as addi. Let’s assume we need to incorporate the addi instruction in our processor design. Answer the following questions: a) Do we need to add any additional logic block to the design presented in the slide? If yes, what do we need to add and where? If not, describe the sequence of the existing logic blocks that will be utilized by the execution of the addi instruction. b) What will be the values (asserted or deasserted) of the following signals generated by the control unit to execute the addi instruction: Branch, MemRead, MemToReg, MemWrtie, ALUSrc, RegWrite? For each signal, provide justifications for your answer. slide no. 26 in Chapter 4 (part 1). is attached to the questions as an image
Q1. Refer to the datapath design on slide no. 26 in Chapter 4 (part 1). While explaining this
datapath, we did not discuss instructions that does immediate arithmetic, such as addi. Let’s
assume we need to incorporate the addi instruction in our processor design. Answer the following
questions:
a) Do we need to add any additional logic block to the design presented in the slide? If yes,
what do we need to add and where? If not, describe the sequence of the existing logic
blocks that will be utilized by the execution of the addi instruction.
b) What will be the values (asserted or deasserted) of the following signals generated by the
control unit to execute the addi instruction: Branch, MemRead, MemToReg, MemWrtie,
ALUSrc, RegWrite? For each signal, provide justifications for your answer.
slide no. 26 in Chapter 4 (part 1). is attached to the questions as an image
![Datapath With Control
PC
MK
Add
Read
address
Instruction
[31-0]
Instruction [31-26]
Instruction [25-21]
Instruction [20-16]
Instruction Instruction [15-11]
memory
Control
Instruction [15-0]
RegDst
Branch
MemRead
MemtoReg
ALUOP
MemWrite
ALUSrc
RegWrite
Read
register 1 Read
data 1
Read
register 2
Write
register
Read
data 2
Write
data Registers
16
Sign-
extend
32
Instruction [5-0]
Shift
left 2
ALU
Addresult
ALU
control
Zero
ALU
result
ALU
Read
data
Address
Write Data
data memory
Chapter 4 - The Processor - 26](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fd64c10e4-ff50-4728-9b40-c2b999a477ac%2F85c5e982-90cd-4cf6-9a88-9cb2964ee90a%2F3om4fq_processed.png&w=3840&q=75)
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Q2. Refer to datapath design on slide no. 26 with added blocks for jump instructions as shown in
slide 33 in Chapter 4 (part 1). Let’s assume a program has 500 instructions. These instructions are
distributed as follows:
R-Type Immediate
arithmetic
(addi)
Load Store Branch Jump
25% 5% 20% 20% 10% 20%
Answer the following questions (show calculations):
a) How many instructions will use instruction memory?
b) How many instructions will use data memory?
c) How many instructions will use the sign extend block?
d) In the clock cycles, where the sign extend block is not required, does it remain idle? If yes,
how? If not, what happens to the output of the block in that cycle?
chapter 4, slide 33 is added as an image needed to solve the question
![릇
Datapath With Jumps Added
MK
MORGAN KAUFHANK
PC
Instruction [25-0]
Add
Read
address
Instruction
[31-0]
Instruction
memory
26
Shift
left 2
Instruction [31-26]
Instruction [25-21]
Instruction [20-16]
Instruction [15-0]
Jump address [31-0]
PC + 4 [31-28]
Control
MX,
28
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOP
MemWrite
ALUSrc
RegWrite
Read
register 1
Read
register
Write
Read
Instruction [15-11] register data 2
Read
data 1
16
Write
data Registers
Sign-
extend
32
Instruction [5-0]
Shift
left 2
MUX-
>Add
ALU
control
ALU
ALU
result
Zero
ALU
result
Address
MUX
Read
data
Write Data
data memory
MUX
MUXO
Chapter 4 - The Processor-33](https://content.bartleby.com/qna-images/question/d64c10e4-ff50-4728-9b40-c2b999a477ac/6cc5365d-ec30-41d6-b0e4-03b4b091e155/1993b3e_processed.png)
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