lem in the pipeline of Teletraan-2. Instruction (2) will be waiting for the result generated by Instruction (1). That means the operand fetch stage cannot fetch the operand of Instruction (2) from R1, unless the write back stage finishes writing the result of Instruction (1) into R1. As a result, the pipeline is stalled for 3 CPU clock cycles. What should we do to alleviate the problem? A. Nothing. We will have to let Instructions (2), (3), and (4) wait. B. We will put Instructions (2), (3), and
When we execute such a program:
(1) R1 = 3 + 5
(2) R2 = R1 / 4
(3) R3 = 4 * 16
(4) R4 = R3 * 2
We realize a problem in the pipeline of Teletraan-2. Instruction (2) will be waiting for the result
generated by Instruction (1). That means the operand fetch stage cannot fetch the operand of
Instruction (2) from R1, unless the write back stage finishes writing the result of Instruction (1)
into R1. As a result, the pipeline is stalled for 3 CPU clock cycles. What should we do to
alleviate the problem?
A. Nothing. We will have to let Instructions (2), (3), and (4) wait.
B. We will put Instructions (2), (3), and (4) in a queue. The first instruction whose operands
are ready will be issued and executed. In this case, Instruction (3) will be the next
instruction executed after Instruction (1).
C. We will put Instructions (2), (3), and (4) in a queue. The first instruction whose operands
are ready will be issued and executed. In this case, Instruction (4) will be the next
instruction executed after Instruction (1).
D. We will let the operand fetch stage fetch the operands of Instruction (2) without waiting,
because we can later add another instruction to correct the error.
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Would the answer be B or C based on the information given?
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