Chapter 3, Problem 3.19P

Enhancement−mode NMOS and PMOS devices both have parameters $L=4\text{μm}$ and . For the NMOS transistor, $V_{TN}=+0.6\text{V}$ , ${\mu }_n=675{\text{cm}}^{\text{2}}\text{/V}-\text{s}$ , and the channel width is $W_n$ ; for the PMOS transistor, $V_{TP}=-0.6\text{V}$ , ${\mu }_p=375{\text{cm}}^{\text{2}}\text{/V}-\text{s}$ , and the channel width is $W_p$ . Design the widths of the two transistors such that they are electrically equivalent and the drain current in the PMOS transistor is $I_D=0.8\text{mA}$ when it is biased in the saturation region at $V_{SG}=5\text{V}$ . What are the values of $K_n,K_p,W_n$ , and $W_p$ ?