8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed. ADDI X1, X2, #5 IF ID EX МЕМ WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (b) What would the final values of registers X3 and X4 be? (c) What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: ADDI X1, X2, #5 MEM WB IF ID EX ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2

8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed. ADDI X1, X2, #5 IF ID EX МЕМ WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (b) What would the final values of registers X3 and X4 be? (c) What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: ADDI X1, X2, #5 MEM WB IF ID EX ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2

Name: 8. Consider the LEGV8 code below. Assume that X1 is initialized to 11
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Description: 8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22.ADDI X1, X2, #5ADD X3, X1, X2ADDI X4, X1, #15ADD X5, X1, X1(a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does no

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a slightly different snippet of IA32 code: 8048396: call 804839b 804839b: ret Suppose that just before the call instruction executes, the value stored in %esp is 0xffffd838. Then what is the value of %eip (the program counter) after the ret instruction executes? a. %eip=0x8048396 b. %eip=0x804839b c. %eip-Oxffffd838 d. %eip=0xffffd834
Assume the initial value for X1 is is 11 and X2 is 22. Suppose we execute the code below on a version of the pipeline from your textbook that does not handle data hazards (i.e., the programmer handles data hazards by inserting NOP instructions where necessary). What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. ADDI X1,X2,#5 ADD X3,X1,X2 ADDI X4,X1,#15 ADD X5,X1,X1
Please solve this two question.In question b draw all cycles one by one in different pages.