8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed. ADDI X1, X2, #5 IF ID EX МЕМ WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (b) What would the final values of registers X3 and X4 be? (c) What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: ADDI X1, X2, #5 MEM WB IF ID EX ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2

8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed. ADDI X1, X2, #5 IF ID EX МЕМ WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (b) What would the final values of registers X3 and X4 be? (c) What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: ADDI X1, X2, #5 MEM WB IF ID EX ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2

Name: 8. Consider the LEGV8 code below. Assume that X1 is initialized to 11
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Description: 8. Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22.ADDI X1, X2, #5ADD X3, X1, X2ADDI X4, X1, #15ADD X5, X1, X1(a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does no

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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A) Identify dependencies add R3, R3, R4 sub R4, R2, beq RO, R2, end addi R4, R4, 12 end: R2, R3 B) insert NOPS add R3, R3, R4 sub R4, R2, R3 beq RO, R2, end nop addi R4, R4, 12 C) reorder for performance
explain this program bus1:mov ax,400add amount, axmov dx,0mov bx,10mov cx,0l222:div bxpush dxmov dx,0mov ah,0inc cxcmp ax,0jne l222l333:pop dxadd dx,48mov ah,2int 21hloop l333;mov am3,amount inc countinc bjmp while_jmp end_ recrd procmov dx,offset msg7mov ah,9int 21h ; print here the whole amountmov ax, amount mov dx,0mov bx,10mov cx,0
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:- We will be implementing a new instruction within the MIPS architecture. New instruction will decrement a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)
For sub $rd, $rs, $rtReg[rd] = Reg[rs] + Reg[rt] - Which resources (blocks) perform a useful function for the given instructions? - Use the following diagram for each instruction and trace its flow(use pen or highlighter) for the execution of that instruction. - List the units that are used for each instruction. (I mainly need help with tracing, please and thank you)
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5. Pipelined datapath has five stages, ie., instruction fetch (IF), decode (ID), execution (EX), memory (MEM), and write back (WB). It has a hazard detection unit. An instruction will be stalled at the decode stage if any of its operands isn't ready. Consider executing the following code on this datapath (1) At the end of fifth cycle of execution, what instruction will be in each of the pipeline stages? (If there is any "bubble" in the pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format. instruction IF instruction lw $r2, 10($1) sub $r4, $13, Sr2 add $r5, Sr6, $7 and Sr8, Sr4,$r5 IF ID EX (2) If the datapath has a forwarding unit to resolve the data hazard, what instruction will be in each of the pipeline stages at the end of the fifth cycle? (If there is any "bubble" in the -pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format: (D MEM EX WB.…
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Q1 [8]. Translate this following C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance. for(i=0; il=j; i+=2) b[i]=a[i]+ a[i+1]; Assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i b C Free R7 R2 R3 j R8 a R1 RO,R10,R11,R12
Consider the fragment of LEGv8 assembly below: Program1 STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPs resulting from this structural hazard by reordering code (reordering the instructions)? 3- Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there? Student should write a justification…
19.Consider the following program. How many clock cycles required to execute the program in the pipelined implementation using stalling? (Concern the control hazard only.) * [Program) i rmov $0,%rax i rmov $0,%rcx 13. LOOP: стр %гсх,%гах je EXIT inc %rax jmp LOOP i7. EXIT: hlt i1. i2. 14. i5. 16. 9 10 11 12
Assume the initial value for X1 is is 11 and X2 is 22. Suppose we execute the code below on a version of the pipeline from your textbook that does not handle data hazards (i.e., the programmer handles data hazards by inserting NOP instructions where necessary). What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. ADDI X1,X2,#5 ADD X3,X1,X2 ADDI X4,X1,#15 ADD X5,X1,X1