SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPs resulting from this structural hazard by reordering code (reordering the instructions)? 3- Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there?

SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPs resulting from this structural hazard by reordering code (reordering the instructions)? 3- Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Let's consider Tomasulo's algorithm. Assume load takes two cycles in execute, add takes three cycles, and a multiple takes seven cycles. Schedule the following code sequence using the instruction status, reservation station, and register status tables and indicate the total number of clock cycles used to complete the code. Show the information tables when the first add has completed and written its result. F2, 0 (x1) FO, F2, F4 F6, FO, F2 T1: fid T2: fmult.d T3: fadd.d T4: fadd.d F2, F4, F2
You are given snapshots of the MIPS pipeline from two successive cycles. For each figure, fill in all the relevant information in each stage, corresponding to the instruction in that stage at that cycle. Remember to specify clearly how control signals are set. Assume $x contains x * 100 (e.g. $1 contains 100). MIPS instructions used: add rd, rs, rt rd = rs + rt or rd, rs, rt rd = rs or rt lw rt, I(rs) rt = Mem[rs + I] (load word) sw rt, I(rs) Mem[rs + I] = rt (store word)
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Consider the following assembly code: Instruction Description LOAD R1, M1 Read data from memory address M1 and store in R1. XOR R2, R1, R1 Logical Ex-OR between contents of R1 with R1 and store result in R2 BNEZ R2, Target1 Jump to Target if R2 is non-Zero ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 AND R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 Targetl: BEZ R2, Target2 Jump to Target if R2 is Zero LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 Save contents of R10 to memory address M4 END
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5. Pipelined datapath has five stages, ie., instruction fetch (IF), decode (ID), execution (EX), memory (MEM), and write back (WB). It has a hazard detection unit. An instruction will be stalled at the decode stage if any of its operands isn't ready. Consider executing the following code on this datapath (1) At the end of fifth cycle of execution, what instruction will be in each of the pipeline stages? (If there is any "bubble" in the pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format. instruction IF instruction lw $r2, 10($1) sub $r4, $13, Sr2 add $r5, Sr6, $7 and Sr8, Sr4,$r5 IF ID EX (2) If the datapath has a forwarding unit to resolve the data hazard, what instruction will be in each of the pipeline stages at the end of the fifth cycle? (If there is any "bubble" in the -pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format: (D MEM EX WB.…
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