2. Consider executing the following assembly code in MIPS five stage (IF, ID, EX, ME, WB) pipeline model:Loop: lw $t0, 0($s1)addi $t0,$t0, 1sw $t0, 0($s1)addi $s1, $s1, 4bne $s1, $s2, Loop a. Assume there is only one memory port, data forwarding is not implemented, and branch instruction stalls untilthe end of the WB stage. Complete the following pipeline execution diagram for one iteration. On average, howmany cycles are needed to finish one original iteration if there are infinite numbers of iterations?12 38 9 10 1112 1315lw $t0, 0(Ss1)addi Sto, $t0, 1sw $t0, 0(Ss1)addi Ss1, $s1, 4bne $$1,$s2, Looplw $t0, 0(Ss1)(next iteration)IFIDEX ME WBb. Indicate all data dependences and their types (i.e., RAW, WAR, or WAW).1416 17 18

In this question, you are given a code snippet in MIPS assembly language and asked to complete a…

Answered: 2. Consider executing the following…

2. Consider executing the following assembly code in MIPS five stage (IF, ID, EX, ME, WB) pipeline mod Loop: lw $t0, 0($s1) addi $t0,$t0, 1 sw $t0, 0(Ss1) addi $s1, $s1, 4 bne $s1, $s2, Loop wwww

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Question

2. Consider executing the following assembly code in MIPS five stage (IF, ID, EX, ME, WB) pipeline model:
Loop: lw $t0, 0($s1)
addi $t0,$t0, 1
sw $t0, 0($s1)
addi $s1, $s1, 4
bne $s1, $s2, Loop

a. Assume there is only one memory port, data forwarding is not implemented, and branch instruction stalls until
the end of the WB stage. Complete the following pipeline execution diagram for one iteration. On average, how
many cycles are needed to finish one original iteration if there are infinite numbers of iterations?
1
2 3
8 9 10 11
12 13
15
lw $t0, 0(Ss1)
addi Sto, $t0, 1
sw $t0, 0(Ss1)
addi Ss1, $s1, 4
bne $$1,$s2, Loop
lw $t0, 0(Ss1)
(next iteration)
IF
ID
EX ME WB
b. Indicate all data dependences and their types (i.e., RAW, WAR, or WAW).
14
16 17 18

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