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The following sequence of instructions will execute on the 5-stage pipelined MIPS datapath: I-MEM Address Instruction OXAO L1: slt $4, $t0, $t1 OXA4 beq $4, $1, L2 OXA8 slt $t4, $t0, $t2 ОХАС beq $14, $1, L2 slt $t4, $t0, $t3 Охво OXB4 beq $t4, $1, L2 OXB8 į L3 L2: addi $t0, $t0, 5 OXBC OXCO j L1 OXC4 L3: List data dependencies for the entire code (i.e. a->b would mean instruction b is dependent on instruction a ): Which data dependencies are hazards? How many clock cycles does it take to execute the entire code for a normal pipelined processor? (i.e. all 5 stages of the last instruction have been completed) How many clock cycles will it take for a 2-issue in-order superscalar pipelined processor to execute the entire code?

The following sequence of instructions will execute on the 5-stage pipelined MIPS datapath: I-MEM Address Instruction OXAO L1: slt $4, $t0, $t1 OXA4 beq $4, $1, L2 OXA8 slt $t4, $t0, $t2 ОХАС beq $14, $1, L2 slt $t4, $t0, $t3 Охво OXB4 beq $t4, $1, L2 OXB8 į L3 L2: addi $t0, $t0, 5 OXBC OXCO j L1 OXC4 L3: List data dependencies for the entire code (i.e. a->b would mean instruction b is dependent on instruction a ): Which data dependencies are hazards? How many clock cycles does it take to execute the entire code for a normal pipelined processor? (i.e. all 5 stages of the last instruction have been completed) How many clock cycles will it take for a 2-issue in-order superscalar pipelined processor to execute the entire code?

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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The following sequence of instructions will execute on the 5-stage pipelined MIPS datapath: I-MEM Address Instruction OXAO L1: slt $t4, $t0, $t1 OXA4 beq $t4, $1, L2 OXA8 slt $14, $t0, $t2 OXAC beq $t4, $1, L2 OXBO slt $t4, $t0, $t3 ОхВ4 beq $t4, $1, L2 OXB8 j L3 OXBC L2: addi $t0, $t0, 5 OXCO j L1 ОХC4 L3: List data dependencies for the entire code (i.e. a->b would mean instruction b is dependent on instruction a ): Which data dependencies are hazards? How many clock cycles does it take to execute the entire code for a normal pipelined processor? (i.e. all 5 stages of the last instruction have been completed) How many clock cycles will it take for a 2-issue in-order superscalar pipelined processor to execute the entire code?
Transcribed Image Text:The following sequence of instructions will execute on the 5-stage pipelined MIPS datapath: I-MEM Address Instruction OXAO L1: slt $t4, $t0, $t1 OXA4 beq $t4, $1, L2 OXA8 slt $14, $t0, $t2 OXAC beq $t4, $1, L2 OXBO slt $t4, $t0, $t3 ОхВ4 beq $t4, $1, L2 OXB8 j L3 OXBC L2: addi $t0, $t0, 5 OXCO j L1 ОХC4 L3: List data dependencies for the entire code (i.e. a->b would mean instruction b is dependent on instruction a ): Which data dependencies are hazards? How many clock cycles does it take to execute the entire code for a normal pipelined processor? (i.e. all 5 stages of the last instruction have been completed) How many clock cycles will it take for a 2-issue in-order superscalar pipelined processor to execute the entire code?
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