### Hazard Avoidance and Instruction Scheduling#### Instructions for Optimizing Pipeline ExecutionTo optimize instruction execution in a pipelined architecture, follow these guidelines:1. **Rearrange Instructions**: Adjust the order of instructions to minimize data hazards. This involves scheduling them such that data dependencies are respected and stalls are reduced.2. **Insert `nop`s**: If hazards are unavoidable, insert `nop` (no operation) instructions to create the necessary stalls. These help in maintaining correct program execution by accommodating data dependency delays.3. **Use of Register S15**: For storing temporary values during modifications, utilize register S15. Making use of additional registers can help manage data flows and dependencies.4. **Instruction Changes**: If rearranging and inserting `nop`s are insufficient, consider altering the instructions themselves to circumvent hazards._Please rewrite the new instruction order below. Once the instructions are finalized, populate the pipeline cycle table accordingly._#### Pipeline Cycle TableThis is a template for tracking instruction execution across pipeline stages and cycles:| Instruction Set | Pipeline Cycle ||-----------------|----------------------------------------------------------|| | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 || **Instruction 1** | | | | | | | | | | | | | || **Instruction 2** | | | | | | | | | | | | | || **Instruction 3** | | | | | | | | | | | | | || **Instruction 4** | | | | | | | | | | | | | |_Update the table above as you execute the modified instruction set to ensure efficient pipeline utilization._ ### Pipeline Simulation ExerciseThis exercise focuses on simulating instruction processing through a pipelined CPU architecture. It explores scenarios involving forwarding and hazard detection.#### a) Number of cycles?Determine the number of pipeline cycles needed for each scenario.#### b) No-forwarding; nops allowedBelow is a table representing the instruction execution in pipeline cycles when no forwarding is implemented. Nops can be inserted to resolve hazards.**Instruction Set | Pipeline Cycle**``` 1 2 3 4 5 6 7 8 9 10 11 12 13 -----------------------------------------```(Empty table for students to fill in.)#### c) Forwarding-allowed; insert stalls/bubbles/nops as required [5 pts]This section allows for forwarding. The table below is for determining where stalls, bubbles, or nops are needed.**Instruction Set | Pipeline Cycle**``` 1 2 3 4 5 6 7 8 9 10 11 12 13 -----------------------------------------```(Empty table for students to fill in.)#### d) If hazard detection is not working, and so no forwarding.Students must simulate what happens when hazard detection fails, which also means no forwarding. Describe each instruction's behavior with comments.**Instruction Set 1:**1. **lw $1, 24($6)**2. **add $2, $3, $1**3. **add $1, $6, $4**4. **and $1, $1, $4**5. **sw $2, 12($2)***(Note: Write in comments what occurs in each instruction step.)*Example: For instruction 1: `add $1, $5, $3 # No action required here`

Name: ### Hazard Avoidance and Instruction Scheduling#### Instructions for
Uploaded: 2024-03-20T06:51:23.000Z
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Description: ### Hazard Avoidance and Instruction Scheduling#### Instructions for Optimizing Pipeline ExecutionTo optimize instruction execution in a pipelined architecture, follow these guidelines:1. **Rearrange Instructions**: Adjust the order of instructions

Data dangersData risks arise whilst commands that exhibit facts dependence modify facts in specific tiers of a pipeline. Ignoring ability statistics hazards can bring about race situations (also termed race hazards). There are 3 situations wherein a facts chance can occur: examine after write (RAW), a real dependencywrite after read (WAR), an anti-dependencywrite after write (WAW), an output dependencyRead after examine (RAR) isn't always a chance case. Consider two instructions i1 and i2, with i1 taking place earlier than i2 in program order. Read after write (RAW)(i2 tries to read a source earlier than i1 writes to it) A study after write (RAW) statistics hazard refers to a state of affairs in which an coaching refers to a end result that has no longer yet been calculated or retrieved. This can arise due to the fact despite the fact that an coaching is finished after a prior training, the earlier instruction has been processed best partly thru the pipeline. ExampleFor example: i1. R2 <- R5 + R3i2. R4 <- R2 + R3The first education is calculating a value to be stored in sign in R2, and the second one is going to apply this price to compute a result for register R4. However, in a pipeline, when operands are fetched for the second operation, the outcomes from the first have not yet been saved, and for this reason a statistics dependency occurs. A information dependency takes place with practise i2, as it's miles depending on the of completion of instruction i1. Write after examine (WAR)(i2 tries to jot down a destination earlier than it's far read by i1) A write after read (WAR) information hazard represents a trouble with concurrent execution. ExampleFor example: i1. R4 <- R1 + R5i2. R5 <- R1 + R2Generic Pipeline bubbling Bubbling the pipeline, also termed a pipeline break or pipeline stall, is a method to preclude data, structural, and branch hazards. As instructions are fetched, control logic determines whether a hazard could/will occur. If this is true, then the control logic inserts no operations (NOPs) into the pipeline. Thus, before the next instruction (which would cause the hazard) executes, the prior one will have had sufficient time to finish and prevent the hazard. If the number of NOPs equals the number of stages in the pipeline, the processor has been cleared of all instructions and can proceed free from hazards. All forms of stalling introduce a delay before the processor can resume execution. Flushing the pipeline occurs when a branch instruction jumps to a new memory location, invalidating all prior stages in the pipeline. These prior stages are cleared, allowing the pipeline to continue at the new instruction indicated by the branch.[3][4] Data hazard There are several main solutions and algorithms used to resolve data hazards: insert a pipeline bubble whenever a read after write (RAW) dependency is encountered, guaranteed to increase latency, or use out-of-order execution to potentially prevent the need for pipeline bubbles use operand forwarding to use data from later stages in the pipeline In the case of out-of-order execution, the algorithm used can be: scoreboarding, in which case a pipeline bubble is needed only when there is no functional unit available the Tomasulo algorithm, which uses register renaming, allowing continual issuing of instructions The task of removing data dependencies can be delegated to the compiler, which can fill in an appropriate number of NOP instructions between dependent instructions to ensure correct operation, or re-order instructions where possible. Operand forwarding[e Example In the following examples, computed values are in bold, while Register numbers are not. For example, to write the value 3 to register 1, (which already contains a 6), and then add 7 to register 1 and store the result in register 2, i.e.: i0: R1 = 6 i1: R1 = 3 i2: R2 = R1 + 7 = 10 Following execution, register 2 should contain the value 10. However, if i1 (write 3 to register 1) does not fully exit the pipeline before i2 starts executing, it means that R1 does not contain the value 3 when i2 performs its addition. In such an event, i2 adds 7 to the old value of register 1 (6), and so register 2 contains 13 instead, i.e.: i0: R1 = 6 i2: R2 = R1 + 7 = 13 i1: R1 = 3