4. Do the following sets cause a data hazard for the 5-stage LEGV8 pipeline?a. i1: ADD X0, X1, X212: ADDX3, XO, X4b. i1: ADD12: ADDc. 11: ADDd.i1: ADD12: SUBX0, X1, X2X3, X1, X4X3, X3, X4XO, X10, X11X12, X0, X13If any of the above have data hazard show the pipeline diagram to resolve it byforwarding. Can all hazards be solved by forwarding?

Instruction fetch :- The programme counter provides the memory address of the location of the…

4. Do the following sets cause a data hazard for the 5-stage LEGV8 pipeline? a. i1: ADD X0, X1, X2 12: ADD X3, XO, X4 b. i1: ADD X0, X1, X2 12: ADD X3, X1, X4 c. i1: ADD X3, X3, X4 d. i1: ADD i2: SUB XO, X10, X11 X12, XO, X13 If any of the above have data hazard show the pipeline diagram to resolve it by forwarding. Can all hazards be solved by forwarding?

4. Do the following sets cause a data hazard for the 5-stage LEGV8 pipeline? a. i1: ADD X0, X1, X2 12: ADD X3, XO, X4 b. i1: ADD X0, X1, X2 12: ADD X3, X1, X4 c. i1: ADD X3, X3, X4 d. i1: ADD i2: SUB XO, X10, X11 X12, XO, X13 If any of the above have data hazard show the pipeline diagram to resolve it by forwarding. Can all hazards be solved by forwarding?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Q2. Refer to datapath design on slide no. 26 with added blocks for jump instructions as shown in slide 33 in Chapter 4 (part 1). Let's assume a program has 500 instructions. These instructions are distributed as follows: R-Type 25% Immediate arithmetic (addi) 5% Load 20% Store 20% Branch 10% Jump 20% Answer the following questions (show calculations): a) How many instructions will use instruction memory? b) How many instructions will use data memory? c) How many instructions will use the sign extend block? d) In the clock cycles, where the sign extend block is not required, does it remain idle? If yes, how? If not, what happens to the output of the block in that cycle?
4. We have the following data for a branching instruction, where T = branch is taken, and N = the bgranch is not taken: TTTTNNNNNNNNNNNTTTTTTTTNNNNNNNNNNTTTT a. what is the success prediction rate for the one bit prediction method? b. what is the success prediction rate for the two bit prediction method? C. compare the two and comment
7. Suppose the GPIO port F of the TIVA board has been properly initialized. A delay function is also provided. The delay is set to 0.1 sec for each function call. #define GPIO_PORTF_DATA_R (*((volatile unsigned long *)O×400253FC)) void Delay(void) {unsigned long volatile time; time = 1600000; // 0.1sec while(time){ time--; } Write embedded C code to generate a square wave on pin 5 of GPIO port F. The frequency of the square wave should be 1 Hz. 0.5 sec
Name 3 types of Pipeline Hazard conditions below: of b) Does a five ståge MIPS pipeline execution of the following sequence instructions generate a hazard? If yes, what type of hazard is it? HOW can you resolve it? sub $s0, St1, $t2 sub $t3, $s0, $t3 sub $t4, Ss0, St4
How many cycles are needed to implement this code assuming the first command is the start of the filling of the pipeline
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For the following assembly code that is vaguely MIPS-like, trace itsexecution in both the R3000 and R4000 pipelines using a Gantt chart (ortable of some kind).LOAD R1, Memory(12340)LOAD R2, Memory(12350)ADD R3, R1, R2 // R3 = R1 + R2ADD R3, R3, R3 // R3 = R3 + R3STORE R3, Memory(12360)
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(a) In MIPS machine language, the R format instructions need an additional field (the “funct” field) to specify the instruction type (“add”, “sub”, etc.). Why can’t this be done using just the 6-bit “op” field, which all MIPS instructions have, instead? (b) Give a sequence of MIPS assembly language instructions that adds the contents of $s0 and $s1, storing the result into $s0, if the contents of $s1 are greater than 6. Otherwise, the contents of $s0 should be incremented by 28. In either case, afterwards the contents of $s0 should be copied into $s2. (c) Suppose that the starting address of an array of words is stored in $s0. Give a MIPS assembly language instruction that loads the contents of the second word in the array into $s1. (d) Suppose that A and B are defined using “A: .word 0”, and “B: .space 100”. Give a sequence of MIPS assembly language instructions that calls a procedure “P” with its two arguments being the contents of A and the address of B, using the standard procedure…
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