In the following, we have a code fragment of LEGV8 assembly: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, Х4 SUB X5, X15, Х4 Assume we run this code on a pipeline CPU that has only one memory for both instructions and data. In this case, there could be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Show where to insert NOPS in the code above to avoid the structural hazard. 2- In your opinion, is there any solution to reduce the number NOPS? Like reordering the instructions. 3- Do you think that we must handle this structural hazard in hardware? You know that data hazards can be avoided by inserting NOPS between assembly instructions. Can we do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there?

In the following, we have a code fragment of LEGV8 assembly: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, Х4 SUB X5, X15, Х4 Assume we run this code on a pipeline CPU that has only one memory for both instructions and data. In this case, there could be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Show where to insert NOPS in the code above to avoid the structural hazard. 2- In your opinion, is there any solution to reduce the number NOPS? Like reordering the instructions. 3- Do you think that we must handle this structural hazard in hardware? You know that data hazards can be avoided by inserting NOPS between assembly instructions. Can we do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there?

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

See similar textbooks

Related questions

Q: Write a minimal sequence of LEGv8 assembly instructions that performs identical operation. The…

A: We need to write code using LEGv8 assembly instructions, to perform y=abs(x).

Q: Consider a HW ISA program P1 with the following Instruction Memory IM: a. fill in the execution…

A: The execution of a program, denoted as "P1," which operates under a specific hardware instruction…

Q: Evaluate the effect of the instruction LDR r1, [r2], #4, given the initial values below. What is the…

A: As ldr r1,[r2], #4 means r1= mem[r2] this means r1=mem[1004] so r1=20 r2 = 1004+4 r2=1008 r3=50…

Q: You may use only the instructions we covered: add, sub, addi, lw, sw and the same rules as…

A: You may use only the instructions we covered: add, sub, addi, lw, sw and the same rules as…

Q: Consider the fragment of LEGv8 assembly below: Program1 STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB…

Q: Using the information below, in assembly language: x BYTE -2, -3, 2, 1 z WORD 3000h, 4000h,…

A: This is related to 8086 and answer is attached in step 2:

Q: Convert the following high-level code into RISC-V assembly language. Assume that the signed integer…

A: Assembly language is a low-level programming language used to communicate directly with a computer's…

Q: Given a partial MIPS assembly code where only two instructions are explicitly given and the location…

A: Answer: Given Full Code: Loop: addi $to, $zero,-50inst2inst3bne $s0, $t1, Loop Machine Code: Raw…

Q: Add control states to the following to implement an exchange-with-memory instruction, xchg. such…

A: Answers:- The Add control states to the following and implement an exchange-with- a memory…

Q: For this problem, suppose that the add (addition) and imul (signed multiplication) instructions are…

A: In the realm of x86-64 assembly programming, the challenge arises when essential instructions like…

Q: Consider the fragment of LEGV8 assembly below: Program1 STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB…

Q: We will be implementing a new instruction within the MIPS architecture. New instruction will…

Question

100%

In the following, we have a code fragment of LEGV8 assembly:
STUR X16,
[X6, #12]
LDUR X16,
[X6, #8]
SUB X7, X5, X4
СВZ X7,
Label
ADD X5,
X1,
X4
SUB X5,
X15,
Х4
Assume we run this code on a pipeline CPU that has only one memory for both instructions and data. In this case, there
could be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another
instruction accesses data.
1- Show where to insert NOPS in the code above to avoid the structural hazard.
2- In your opinion, is there any solution to reduce the number NOPS? Like reordering the instructions.
3- Do you think that we must handle this structural hazard in hardware? You know that data hazards can be avoided by
inserting NOPS between assembly instructions. Can we do the same with this structural hazard? If so, explain how. If not,
explain why not.
4- If we run the code above on a single-cycle computer, what kind of hazards are there?

Expert Solution

This question has been solved!

Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.

This is a popular solution!

SEE SOLUTION Check out a sample Q&A here

Step 1

VIEW

Step 2

VIEW

Trending now

This is a popular solution!

Step by step

Solved in 2 steps with 2 images

SEE SOLUTION Check out a sample Q&A here

Similar questions

Write the MIPS assembly instructions for the following high-level statement X[i] = A[B[i]] +C[i+4]; Where A, B, C and X are arrays whose starting addresses are available in $1, $2, $3, $4 registers respectively. The value ‘i’ is present in register $5. Need solution for the above question
Write a portion of assembly code that uses shifts and rotates to separate each byte of EAX and store them in order from most to least significant in BL, BH, DL, and DH respectively. Your code must only use shifts, rotates and the MOV instruction. Once your code is finished executing, the values of the registers should be: BL = the first and highest byte of EAX (most significant) BH = the second byte of EAX DL = the third byte of EAX DH = the fourth and lowest byte of EAX (least significant)
3 C language into LC-3 Assembly Language
Q1 [8]. Translate this following C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance. for(i=0; il=j; i+=2) b[i]=a[i]+ a[i+1]; Assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i b C Free R7 R2 R3 j R8 a R1 RO,R10,R11,R12
Consider the fragment of LEGv8 assembly below: Program1 STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPs resulting from this structural hazard by reordering code (reordering the instructions)? 3- Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there? Student should write a justification…