Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Question
Chapter 4.3, Problem 4.22PP
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
Combinational circuits and HCL expressions:
- The computational blocks are been constructed by accumulating several logic gates into network.
- The restrictions are been shown below:
- Each of input for logic gate should be connected to any one shown below:
- One of system inputs, that is identified as primary inputs.
- Output connection for some element in memory.
- Output of some logic gate.
- Outputs obtained from more than two logic gates could not be linked together.
- The wire would be driven to different voltages.
- It can cause malfunction in circuit.
- The network should not have cycles.
- The loops in circuit can cause ambiguity in function
computed by network.
- The loops in circuit can cause ambiguity in function
- Each of input for logic gate should be connected to any one shown below:
- The “HCL” denotes a hardware control language that is used for describing control logic of different processor designs.
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solutionStudents have asked these similar questions
subject : computer architectures and organization (computer science)
(c) The following Sigma 16 program has been loaded into memory at address 0000:
load R3,y[RO]
load R4,x[RO]
lea R5, 2[RO]
sub R1,R4,R3
mul R2,R1,R5
store R2,w[RO]
trap RO,RO,RO
x data 10
y data 12
w data 0
Show the content of the memory writing hexadecimal representation and using a
table with 3 columns: the memory address, the contents of that memory address,
and an explanation of what "the content (of that memory address) means". As a
reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c.
And here the opcodes for RX instructions: lea 0, load 1, store 2.
[7]
(a) An instruction at address 021 in the basic computer has I-0, an operation code of the AND
instruction, and an address part equal to 083 (all numbers are in hexadecimal). The memory word at
address 083 contains the operand B8F2 and the content of AC is A937. Go over the instruction cycle
and determine the contents of the following registers at the end of the execute phase: PC, AR, DR, AC,
and IR. Repeat the problem six more times starting with an operation code of another memory-
reference instruction.
Chapter 4 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
Ch. 4.2 - Prob. 4.11PPCh. 4.2 - Prob. 4.12PPCh. 4.3 - Prob. 4.13PPCh. 4.3 - Prob. 4.14PPCh. 4.3 - Prob. 4.15PPCh. 4.3 - Prob. 4.16PPCh. 4.3 - Prob. 4.17PPCh. 4.3 - Prob. 4.18PPCh. 4.3 - Prob. 4.19PPCh. 4.3 - Prob. 4.20PPCh. 4.3 - Prob. 4.21PPCh. 4.3 - Prob. 4.22PPCh. 4.3 - Prob. 4.23PPCh. 4.3 - Prob. 4.24PPCh. 4.3 - Prob. 4.25PPCh. 4.3 - Prob. 4.26PPCh. 4.3 - Prob. 4.27PPCh. 4.4 - Prob. 4.28PPCh. 4.4 - Prob. 4.29PPCh. 4.5 - Prob. 4.30PPCh. 4.5 - Prob. 4.31PPCh. 4.5 - Prob. 4.32PPCh. 4.5 - Prob. 4.33PPCh. 4.5 - Prob. 4.34PPCh. 4.5 - Prob. 4.35PPCh. 4.5 - Prob. 4.36PPCh. 4.5 - Prob. 4.37PPCh. 4.5 - Prob. 4.38PPCh. 4.5 - Prob. 4.39PPCh. 4.5 - Prob. 4.40PPCh. 4.5 - Prob. 4.41PPCh. 4.5 - Prob. 4.42PPCh. 4.5 - Prob. 4.43PPCh. 4.5 - Prob. 4.44PPCh. 4 - Prob. 4.45HWCh. 4 - Prob. 4.46HWCh. 4 - Prob. 4.47HWCh. 4 - Prob. 4.48HWCh. 4 - Modify the code you wrote for Problem 4.47 to...Ch. 4 - In Section 3.6.8, we saw that a common way to...Ch. 4 - Prob. 4.51HWCh. 4 - The file seq-full.hcl contains the HCL description...Ch. 4 - Prob. 4.53HWCh. 4 - The file pie=full. hcl contains a copy of the PIPE...Ch. 4 - Prob. 4.55HWCh. 4 - Prob. 4.56HWCh. 4 - Prob. 4.57HWCh. 4 - Our pipelined design is a bit unrealistic in that...Ch. 4 - Prob. 4.59HW
Knowledge Booster
Similar questions
- (e) Instruction(s) to copy contents at one memory location to another: C[g] =A[i+j-3). Assume i, j,g values are in registers x5, x6, x7. Assume base address in memory of Array data structures 'A, B' (or address in memory of 'A[O]' and 'B[O]') are stored in Registers x28, 29• In RISCV, only load and store instructions access memory locations • These instructions must follow a 'format' to access memory • Assume a 32 bit machine in all problems unless asked to assume otherwisearrow_forward3arrow_forward3. Verify the operation of instruction. JMP BX Assume the content of BX is 0010 H.arrow_forward
- Question 20 Write 2 different solutions, each consists of ONE correct MIPS instruction (Pseudo-instructions are NOT allowed) to store Oxfffffff in $a0:arrow_forwardProblem I ( Assembler ) Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x. Assumption : MyArray base address is store in register $S1. Feel free to use instruction li or si. li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4. C code for ( i = 0,1 < 10 , i ++ ) { MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ; Sub10 ( MyArray [ i ]; } Sub10 ( x ) { Return ( x - 10 ) ; } Code in Assembly Language: sub10(int): ; Implementation of the sub10() function push rbp mov rbp, rsp mov DWORD PTR [rbp-4], edi mov eax, DWORD PTR [rbp-4] sub eax, 10 pop rbp ret main: ; Main function Implementation push rbp mov rbp, rsp sub rsp, 64 mov…arrow_forwardQuestion 4 Compare between the following sequence of instructions. (6.1: Set 1 MOV RO, #0x47 MOV RI, #0x47 Set 2 MOV RO, #0x47 b. MOV RI, #0x47 TEQ RO, RI a. a. b. с. EORS RO, RI ii. What is the content of the registers and flags after execution of the instruction? Code set I MOV RO, #0x47 b. MOV RI, #0x47 RO RI C V а. с. EORS RO, RI Code set 2 RO RI C V MOV RO, #0x47 MOV RI, #0x47 TEQ RO, RI a. b. с.arrow_forwardA.20 [20/20/20] We are designing instruction set formats for a load-store archi- tecture and are trying to decide whether it is worthwhile to have multiple offset lengths for branches and memory references. The length of an instruction would be equal to 16 bits + offset length in bits, so ALU instructions will be 16 bits. Figure A.31 contains data on offset size for the Alpha architecture with full opti- mization for SPEC CPU2000. For instruction set frequencies, use the data for MIPS from the average of the five benchmarks for the load-store machine in Fig- ure A.27. Assume that the miscellaneous instructions are all ALU instructions that use only registers. Exercises by Gregory D. Peterson A-53 Number of offset magnitude bits 0 1 Cumulative data references Cumulative branches 30.4% 0.1% 33.5% 2.8% 2 35.0% 10.5% 3 40.0% 22.9% 4 47.3% 36.5% 5 54.5% 57.4% 6 60.4% 72.4% 7 66.9% 85.2% 8 71.6% 90.5% 9 73.3% 93.1% 10 74.2% 95.1% 11 74.9% 96.0% 12 76.6% 96.8% 13 87.9% 97.4% 14 91.9% 98.1%…arrow_forwardQ1: Determine the physical address of the source operand base on the Based Indexed Addressing Mode. The MOV instruction MOV AX, [BX].[16A0] [SI] The contents of IP, CS and DS are 0120, A342p, and 2C60, respectively. Also, the contents of BX and SI are 6752, and C344, respectively. Explain by the draw the registers and the logical of the system memory in the before execution and after execution. Note: the content of PA is 2B7C and the coding of this instruction is XXXXarrow_forwardQuestion 3 Execute the following instruction by the following SS and show the execution of A- Inorder Issue & In Order Completion B- Inorder Issue & Out of Order Completion Div / ADD / Sw Mul F0 , F2 , F4 Add F9 , F10 , FO Div F9, F23 , F25 Sub F19 , F15 , F9 Div F44 , F25 , F90 Sw F0 , 5(R1) Sub F13, F15 , F16 ai a2 a3 f1 di Other f2 d2 S2 elarrow_forward(d) You are working on a redesign of a simple 16-bit computer which supports at most 64 kilobytes of memory. Currently, memory is word-addressed and all memory accesses load or store a 16-bit value. For example, LDA Ox6502 loads a 16-bit value from address Ox6502 into register A. The change is to support additionally 8-bit accesses, thanks to an expanded machine language (already designed by a colleague) which now supports instructions such as: ; load 16 bits from addr 6502 into A ; load 8 bits from addr 6502 into A LDAW Ox6502 LDAB Ox6502 Outline, at a high level, how you would bring about this change in the CPU design, and mentioning any difficulties you expect to encounter.arrow_forwardi need ans very very fast in 20 min and thank you | ᴅʏʙᴀʟᴀ ?✨ | microprocessor 8085؛arrow_forwardarrow_back_iosSEE MORE QUESTIONSarrow_forward_ios
Recommended textbooks for you
- Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
- C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education