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Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Question
Chapter 4.3, Problem 4.18PP
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
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Problem 1.8 The following code segment, consisting of six instructions, needs to be
executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I)
xC(I) for 0 ≤ I≤ 63.
Load R1, B(I)
/R1 - Memory (a + I)/
Load R2, C(I)
Multiply R1, R2
Load R3, A(I)
Add R3, R1
Store D(I), R3
t
/R2 Memory (8 + 1)/
/R1 - (R1) × (R2)/
/R3
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Memory (7 + I)/
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/R3 (R3) + (R1)/
/Memory (0 + I) ← (R3)/
where R1, R2, and R3 are CPU registers, (R1) is the content of R1, a, ß,7, and are
the starting memory addresses of arrays B(1), C(I), A(I), and D(I), respectively. Assume
four clock cycles for each Load or Store, two cycles for the Add, and eight cycles for the
Multiply on either a uniprocessor or a single PE in an SIMD machine.
(a) Calculate the total
ber of CPU cycles needed to execute the above code seg-
ment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring
all other time delays.
(b) Consider the use of an SIMD computer with 64 PEs to execute the above…
(c) The following Sigma 16 program has been loaded into memory at address 0000:
load R3,y[RO]
load R4,x[RO]
lea R5, 2[RO]
sub R1,R4,R3
mul R2,R1,R5
store R2,w[RO]
trap RO,RO,RO
x data 10
y data 12
w data 0
Show the content of the memory writing hexadecimal representation and using a
table with 3 columns: the memory address, the contents of that memory address,
and an explanation of what "the content (of that memory address) means". As a
reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c.
And here the opcodes for RX instructions: lea 0, load 1, store 2.
[7]
Problem 1.8 The following code segment, consisting of six instructions, needs to be
executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I)
xC(I) for 0 ≤ I ≤ 63.
Load R1, B(I)
/R1 - Memory (a + I)/
Load R2, C(I)
Multiply R1, R2
Load R3, A(I)
Add R3, R1
Store D(I), R3
t
/R2 Memory (8 + 1)/
/R1 - (R1) × (R2)/
/R3
-
Memory (7 + I)/
-
/R3 (R3) + (R1)/
/Memory (0 + I) ← (R3)/
where R1, R2, and R3 are CPU registers, (R1) is the content of R1, a, ß,7, and are
the starting memory addresses of arrays B(1), C(I), A(I), and D(I), respectively. Assume
four clock cycles for each Load or Store, two cycles for the Add, and eight cycles for the
Multiply on either a uniprocessor or a single PE in an SIMD machine.
(a) Calculate the total
ber of CPU cycles needed to execute the above code seg-
ment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring
all other time delays.
(b) Consider the use of an SIMD computer with 64 PEs to execute the above…
Chapter 4 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
Ch. 4.2 - Prob. 4.11PPCh. 4.2 - Prob. 4.12PPCh. 4.3 - Prob. 4.13PPCh. 4.3 - Prob. 4.14PPCh. 4.3 - Prob. 4.15PPCh. 4.3 - Prob. 4.16PPCh. 4.3 - Prob. 4.17PPCh. 4.3 - Prob. 4.18PPCh. 4.3 - Prob. 4.19PPCh. 4.3 - Prob. 4.20PPCh. 4.3 - Prob. 4.21PPCh. 4.3 - Prob. 4.22PPCh. 4.3 - Prob. 4.23PPCh. 4.3 - Prob. 4.24PPCh. 4.3 - Prob. 4.25PPCh. 4.3 - Prob. 4.26PPCh. 4.3 - Prob. 4.27PPCh. 4.4 - Prob. 4.28PPCh. 4.4 - Prob. 4.29PPCh. 4.5 - Prob. 4.30PPCh. 4.5 - Prob. 4.31PPCh. 4.5 - Prob. 4.32PPCh. 4.5 - Prob. 4.33PPCh. 4.5 - Prob. 4.34PPCh. 4.5 - Prob. 4.35PPCh. 4.5 - Prob. 4.36PPCh. 4.5 - Prob. 4.37PPCh. 4.5 - Prob. 4.38PPCh. 4.5 - Prob. 4.39PPCh. 4.5 - Prob. 4.40PPCh. 4.5 - Prob. 4.41PPCh. 4.5 - Prob. 4.42PPCh. 4.5 - Prob. 4.43PPCh. 4.5 - Prob. 4.44PPCh. 4 - Prob. 4.45HWCh. 4 - Prob. 4.46HWCh. 4 - Prob. 4.47HWCh. 4 - Prob. 4.48HWCh. 4 - Modify the code you wrote for Problem 4.47 to...Ch. 4 - In Section 3.6.8, we saw that a common way to...Ch. 4 - Prob. 4.51HWCh. 4 - The file seq-full.hcl contains the HCL description...Ch. 4 - Prob. 4.53HWCh. 4 - The file pie=full. hcl contains a copy of the PIPE...Ch. 4 - Prob. 4.55HWCh. 4 - Prob. 4.56HWCh. 4 - Prob. 4.57HWCh. 4 - Our pipelined design is a bit unrealistic in that...Ch. 4 - Prob. 4.59HW
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