Explanation Given: V D D = 1.8 V The threshold voltages are V T N D = 0.4 V and V T N L = − 0.6 V k n ' = 100 μA/V 2 The maximum inverter power dissipation is 0.2 mW The output voltage is 0.08 V when v 1 = 1.8 V Calculation: The circuit is shown below. The maximum power P D , max dissipated across NMOS invertor is, P D , max = i D , max . V D D Here, i D , max is the maximum drain current and V D D is the biased voltage. Substitute the values, the maximum drain current i D , max is, i D , m a x = P D , max V D D = 0.02 m 1.8 = 0.02 × 10 − 3 1.8 = 11.11 μA Also, the maximum drain current i D , max is, i D , max = k n ' 2 . ( W L ) D ( 2 ( v 1 − V T N D ) v O − v O 2 ) Here, ( W L ) D is the width ( W ) to length ( L ) ratio of the driver of the NMOS invertor, v 1 is the input voltage, V T N D is the threshold voltage of the NMOS, v O is the output voltage across the invertor, and k n ' is the process parameter. To find the width to length ratio ( W L ) D of the driver transistor of the depletion mode NMOS invertor, substitute the values, i D , max = k n ' 2 . ( W L ) D ( 2 ( v 1 − V T N D ) v O − v O 2 ) 11.11 μ = 100 μ 2 ( W L ) D ( 2 ( 1.8 − 0.4 ) ( 0.08 ) − ( 0.08 ) 2 ) ( 11.11 × 10 − 6 ) ( 2 100 × 10 − 6 ) ( 1 ( 2 ( 1.8 − 0.4 ) ( 0.08 ) − ( 0.08 ) 2 ) ) = ( W L ) D 10.2 = ( W L ) D In saturation region the load transistor parameter K L , and the driver transistor parameter K D of a depletion mode NMOS invertor, are related as, K D [ 2 ( V D D − V T N D ) ( v o ) − v o 2 ] = K L ( 0 − ( − V T N L ) ) 2 Substitute 1

MICROELECT. CIRCUIT ANALYSIS&DESIGN (LL)

4th Edition

ISBN: 9781266368622

Author: NEAMEN

Publisher: MCG

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MICROELECT. CIRCUIT ANALYSIS&DESIGN (LL)

Ch. 16 - Consider the NMOS inverter with resistor load in...Ch. 16 - The enhancementload NMOS inverter in Figure...Ch. 16 - Prob. 16.3EP Ch. 16 - Prob. 16.4EP Ch. 16 - Consider the NMOS inverter with enhancement load,...Ch. 16 - Prob. 16.2TYU Ch. 16 - (a) Consider the results of Exercise Ex 16.1....Ch. 16 - Prob. 16.5EP Ch. 16 - Prob. 16.6EP Ch. 16 - (a) Design a threeinput NMOS NOR Logic gate with...

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The design parameters the inverter with the given conditions

Solution Summary: The author explains the design parameters of the inverter with the given conditions. The maximum power dissipation is 0.2mW

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