Chapter 16, Problem 16.11EP

Design the width−to−length ratios of the transistors in the static CMOS logic circuit of Figure 16.40. Symmetrical switching times are desired and the switching times should correspond to the basic CMOS inverter. (Ans. All NMOS devices, $W_n=2W$ ; $W_p\left(M_{PA}\right)=W_p\left(M_{PB}\right)=W_p\left(M_{PC}\right)=4W$ ; $W_p\left(M_{PD}\right)=W_p\left(M_{PE}\right)=8W$ )