Upload answer sheets Test time left: 0: Consider a 8-way set associative mapped cache of size 64 MB with block size 8 KB. The size of main memory is 32 GB. Find- i) Number of bits in physical address ii) Number of bits in block-offset i) Number of lines in cache iv) Number of sets in cache Tag diroctoni rizo

Upload answer sheets Test time left: 0: Consider a 8-way set associative mapped cache of size 64 MB with block size 8 KB. The size of main memory is 32 GB. Find- i) Number of bits in physical address ii) Number of bits in block-offset i) Number of lines in cache iv) Number of sets in cache Tag diroctoni rizo

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Computer science question
A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1a) What is the number of cache lines? Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits).
Answer part d only
Cache Mapping a. A computer system has a main memory with 128 blocks and a cache with 32 blocks. If it uses direct mapping, how many main memory blocks can be mapped to a single cache block? b. In a set-associative cache with 64 blocks and divided into 4 sets, determine the associativity of each set. c. For a fully associative cache with 256 blocks, how many sets are there?
Consider a cache with 128 blocks. The block size is 32 bytes. Find the number of tag bits, index bits, and offset bits in a 32-bit address if you design it as a) Direct-mapped b) 8-way Set Associative
Assume that you have a direct-mapped cache with 16 indices and each block can contain 32 words. Assuming that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions: a). How many bits in each address are used for its tag? bits b). Compute the total number of bits required to implement this cache, including valid bits, tag bits and bits used for data. bits
Consider a 2-block fully associative cache. The following blocks from main memory are accessed which need to be mapped to cache: P, Q, P, R. Which block is replaced from the cache when the last block (block R) is accessed? Assume FIFO replacement policy.
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7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 Op. lw lw SW lw SW lw lw SW lw lw hits = misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate = miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003
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