led. The addresses are given in the hexadecimal base. Also, leas LRU) (a replacement scheme in which the block replaced is the een unused for the longest time) policy is used to resolve conflic

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Beginning from power on, the following byte-addressed cache references are
recorded. The addresses are given in the hexadecimal base. Also, least recently
used (LRU) (a replacement scheme in which the block replaced is the one that
has been unused for the longest time) policy is used to resolve conflicts (if any)
Address
Нех
00
06
15
06
F8
AD
701
(D)For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or
a miss, and (3) which bytes were replaced (if any).
(E) What is the hit ratio?
(F) List the final state of the cache, with each valid entry represented as a
record of <index, tag, data>. For example;
<0, 3, Mem[0xCo00)-Mem[0XC1F]>.
(G) Finally, give a diagrammatic representation showing the implementation of
this n-way set associative cache memory, showing the extra comparators,
the multiplexer required, etc.
Transcribed Image Text:Beginning from power on, the following byte-addressed cache references are recorded. The addresses are given in the hexadecimal base. Also, least recently used (LRU) (a replacement scheme in which the block replaced is the one that has been unused for the longest time) policy is used to resolve conflicts (if any) Address Нех 00 06 15 06 F8 AD 701 (D)For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). (E) What is the hit ratio? (F) List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. For example; <0, 3, Mem[0xCo00)-Mem[0XC1F]>. (G) Finally, give a diagrammatic representation showing the implementation of this n-way set associative cache memory, showing the extra comparators, the multiplexer required, etc.
Questions based on Chapter 5 <points 2X1.5 +15 + 5>
1. When simulating a cache (by hand or by computer), we need to make sure
we account for the effect of byte addressing and multiword blocks in
determining into which cache block a given address maps (Show your
complete work for all the parts).
Now, solve the following problems:
(A) Given a 1024-byte direct-mapped cache with a block size of 64 bytes,
word is of size 32 bits and a 32 bit memory address; find what the
byte address 20010 maps into?
(B) Also determine what an address maps into if address 20010 is given to
be a word address?
2. <15 points distribution: 2+2+2+3+2+2+2 points> (Show your complete work
for all the parts).
For a set associative cache design with a 64-bit address, the following bits
of the address are used to access the cache.
Index
Offset
Tag
63-9
8-6
5-0
(A) What is the cache block size (in words, remember a word is 32 bits)?
(B) How many blocks and number of sets does the cache have?
(C) What is the ratio between total bits required for such a cache
implementation over the data storage bits?
Transcribed Image Text:Questions based on Chapter 5 <points 2X1.5 +15 + 5> 1. When simulating a cache (by hand or by computer), we need to make sure we account for the effect of byte addressing and multiword blocks in determining into which cache block a given address maps (Show your complete work for all the parts). Now, solve the following problems: (A) Given a 1024-byte direct-mapped cache with a block size of 64 bytes, word is of size 32 bits and a 32 bit memory address; find what the byte address 20010 maps into? (B) Also determine what an address maps into if address 20010 is given to be a word address? 2. <15 points distribution: 2+2+2+3+2+2+2 points> (Show your complete work for all the parts). For a set associative cache design with a 64-bit address, the following bits of the address are used to access the cache. Index Offset Tag 63-9 8-6 5-0 (A) What is the cache block size (in words, remember a word is 32 bits)? (B) How many blocks and number of sets does the cache have? (C) What is the ratio between total bits required for such a cache implementation over the data storage bits?
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