Design a cache with cache size of 128K bytes, block (line) size of 8 words, and word size of 4 bytes. Consider a computer with 64-bit physical address. The cache is addressed by physical address. a. Determine the tag array size (in bytes) for three cache implementations (direct-mapped, 16-way, set-associative, and fully associative). b. Using the tag array sizes computed in (a), compare the percentage overhead of different cache designs. In other words, compute the percentage of the tag array compared to the original cache design (128K), and identify the best, moderate and worst cache implementations in terms of tag area overhead. c. Why would anyone use the implementation you identified in (b) with worst area (tag array) overhead? In other words, identify a scenario when a designer will use the cache implementation that you identified in (b) with worst area overhead.
Design a cache with cache size of 128K bytes, block (line) size of 8 words, and word size of 4 bytes. Consider a computer with 64-bit physical address. The cache is addressed by physical address.
a. Determine the tag array size (in bytes) for three cache implementations (direct-mapped, 16-way, set-associative, and fully associative).
b. Using the tag array sizes computed in (a), compare the percentage overhead of different cache designs. In other words, compute the percentage of the tag array compared to the original cache design (128K), and identify the best, moderate and worst cache implementations in terms of tag area overhead.
c. Why would anyone use the implementation you identified in (b) with worst area (tag array) overhead? In other words, identify a scenario when a designer will use the cache implementation that you identified in (b) with worst area overhead.
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