5. Suppose a byte-addressable computer using set-associate cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 16 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?

5. Suppose a byte-addressable computer using set-associate cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 16 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?

Name: 5. Suppose a byte-addressable computer using set-associative cache ha
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Description: 5. Suppose a byte-addressable computer using set-associative cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 16 bytes.a) If this cache is 2-way set associative, what is the format of a memory address as

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
What is the difference between a cache that is entirely associative and a cache that is directly mapped?
QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)
Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
Cache Mapping a. A computer system has a main memory with 128 blocks and a cache with 32 blocks. If it uses direct mapping, how many main memory blocks can be mapped to a single cache block? b. In a set-associative cache with 64 blocks and divided into 4 sets, determine the associativity of each set. c. For a fully associative cache with 256 blocks, how many sets are there?
1. A memory system with cache memory has an 8-bit word address. The direct-mapped mapping technique is used. The cache memory has 8 cache blocks. Each cache block contains 4 words. How many bits are used for the tag field in the cache? 2. A memory system with cache memory has an 8-bit word address. The direct-mapped mapping technique is used. The cache memory has 8 cache blocks. Each cache block contains 4 words. Which cache block is word 43 mapped to? 3. A memory system with cache memory has an 8-bit word address. The direct-mapped mapping technique is used. The cache memory has 8 cache blocks. Each cache block contains 4 words. What is the tag of word 43?
5. A computer has an L1 and L2 cache, backed up by DRAM which is backed up by virtual memory. The TLB and L1 caches have hit times of .5 ns. The TLB's backup is the page table in DRAM while L1 cache's backup is an L2 cache. The L2 cache has a hit time of 1.5 ns. DRAM has a hit time of 10 ns. Swap space has a hit time of 2,500,000 ns. The hit rates are: TLB: 98.8%, L1: 91.5%, L2: 97.7%, DRAM: 99.9998% and swap space 100%. What is the effective access time?
Suppose a computer using direct mapped cache has 224 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?