Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? Word within block 00 01 10 11 2016 6116 C116 2116 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive?

Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? Word within block 00 01 10 11 2016 6116 C116 2116 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a. What is the cache block size (in words)? b. How many entries does the cache have? Offset 4-0 c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we…
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
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The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220 2A122C B14408 B14428 2A122C
c) The table below represents 5 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (F316). Word 10 Line# Tag Word Word 11 Word 00 01 110101 12 34 56 78 010101 54 32 6A D3 000111 29 8C ED F3 001100 33 A2 20 C8 4 110011 9A BC D8 FO