I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?

Imagine we have a small computer which contains a simplified version of a CPU and RAM. The CPU can execute a single program that is stored in the RAM, and while running the program it can access 3 memory locations: its internal register AL, and two RAM locations that we'll call address 1 and address 2. Since this is a simplified computer it is able to skip some of the steps to access memory that are in our textbook, but accessing RAM still takes longer than accessing AL. The only values this computer is capable of storing in memory are unsigned bytes (8 bit binary numbers), and when it starts running a program all 3 of its memory locations initially contain the value 00000000.  Here is a list of all of the instructions our imaginary computer can perform: Write [number] to AL This instruction takes the operand [number], which must be an 8-bit binary number, and puts it into AL. This overwrites whatever was in AL previously. It takes 3 cycles to complete: 1 cycle each to fetch, decode,…

0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory 0011 = Load AC (the accumulator register) from an I/O device 0111 = Store AC to an I/O device With these instructions, a particular I/O device is identified by replacing the 12-bit address portion with a 12-bit device number. Remember that a number ending with a small ‘h’ means the number is a hexadecimal number. What is the hexadecimal string that expresses the following instructions? Load AC from memory location 62h.  Add the contents of memory location 451h to AC.  Store AC to memory location 8h.  Store AC to I/O device number 8h.

Q.1.     A computer uses a memory unit with 1024 K words of 32 bits each (as shown in the figure below). A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part (15). How many bits are there in the operation code, the register code part, and the address part? Draw the instruction word format and indicate the number of bits in each part? How many bits are there in the data and address inputs of the memory?

Convert the following Compact Memory Notation diagram into an Array Memory Notation diagram. Assume the addresses are 4-bit binary values and the data are 8-bit binary values. Hint: The solution to this question is simply the reformatted diagram in Array Notation.

Part 1 A small computer on a smart card has four page frames. At the first clock tick, the R bits are 0111 (page 0 is 0, the rest are 1). At subsequent clock ticks, the values are 1011, 1010, 1101, 0010, 1010, 1100, and 0001. If the aging algorithm is used with an 8-bit counter, give the values of the four page counters after the last tick.   Part 2 A computer has four page frames. The time of loading, time of last access, and the R and M bits for each page are as shown below (the times are in clock ticks): Page Loaded Last Referenced R M 0 176 330 1 0 1 280 315 0 1 2 190 320 0 0 3 160 335 1 1   (a) Which page will NRU replace? (b) Which page will FIFO replace? (c) Which page will LRU replace? (d) Which page will second chance replace?

Suppose the RAM for a certain computer has 4M words, where each word is 16 bits long. What is the capacity of this memory expressed in bytes? If this RAM is byte addressable, how many bits must an address contain? If this RAM is word addressable, how many bits must an address contain?

Question 6 Suppose you have a RISC machine with a 1.6 GHz clock (i.e., the clock ticks 1.6 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: set reg, immed 2 clock cycle 2 clock cycles 2 clock cycle 4 clock cycles 3 clock cycles loop label add reg, immed add reg, reg load reg, mem Assume that the following code franent is used to sum the element of a numeric array. If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 5 ms? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired. ri, e r2, MAX_SIZE ;initialize loop counter r3, @list initialize sum set set set initialize array pointer more: load…

Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, immed ; 3 clock cycles LOAD reg, mem ; 4 clock cycles ADD reg, reg ; 3 clock cycles ADD reg, immed ; 2 clock cycles LOOP _LabelName ; 8 clock cycles Assume that the following code fragment is used to sum the element ofa numeric array. SET reg1, O SET reg2, MAX_SIZE ;initialize loop counter SET reg3, @list ;initialize array pointer ProcessArray: LOAD reg4, [reg3] ;fetch current list element ADD reg1, reg4 ADD reg3, 4 LOOP _ProcessArray ;auto-decrement reg2, jump to more if reg2 # 0 If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 4.4 milliseconds (ms)? Round your answer to the…

mcq question The Physical address of the String Destination Memory Reference is:       DS:DI, DS:SI, and DS:BX       SS:SP, and SS:BP       ES:DI only       ES:DI and ES:SI