Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 1 011 000101 100 001000 101 100010 110 010111 111 110110

Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 1 011 000101 100 001000 101 100010 110 010111 111 110110

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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If the RAM has a two byte data word and address bits are grouped for direct mapping with a cache memory as follow: 14 bits 9 bits 5 bits When it is read from RAM to cache what other words come with the word whose address is AFF0ODC O a. All words from address 00FFOOC0 to 00FF0ODF O b. All words from address 00FF00C0 to 00FF00CF O C. All words from address 00FF0ODC to 0OOFF0ODF d. All words from address 00FF0ODO to 00FF0ODF
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Given a MIPS processor with a direct-mapped data cache. On this processor the following code is running: sum = 0; for (i=0; i<4; i++) sum = sum + A[i) + A[i+2]; 'A' is an array of (32-bit) integers, word-aligned in memory. All other variables used in this program are already located in registers. What is the data cache hit-rate (in number of percents) for this program, assuming that the cache has a block size of 1 word? Answer:
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