For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes.  What is the ratio between total bits required for such a cache implementation over the data storage bits?

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 For a direct-mapped cache design with a 32-bit address, the following bits of
the address are used to access the cache. We assume that each word has 4 bytes. 

What is the ratio between total bits required for such a cache
implementation over the data storage bits?

Tag Index
Offset
Block offset Byte offset
31–12 11-6
5-2
1-0
Transcribed Image Text:Tag Index Offset Block offset Byte offset 31–12 11-6 5-2 1-0
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